Result Details
Packet Header Analysis and Field Extraction for Multigigabit Networks
Packet header analysis and extraction of header fields needs to beperformed in all network devices. As network speed is increasingquickly, high speed packet header processing is required. We propose anew architecture of packet header analysis and fields extractionintended for high-speed FPGA-based network applications. Thearchitecture is able to process 20 Gbps network links with less than 12percent of available resources of Virtex 5 110 FPGA. Moreover, thepresented solution can balance between network throughput and consumedhardware resources to fit application needs. The architecture forpacket header processing is generated from standard XML protocol schemeand is strongly optimised for resource consumption and speed by anautomatic HDL code generator. Our solution also enables to change theset of extracted header fields on-line without FPGA reconfiguration.
protocol analysis, extraction, networks, XML, FPGA
@inproceedings{BUT33781,
author="Petr {Kobierský} and Jan {Kořenek} and Libor {Polčák}",
title="Packet Header Analysis and Field Extraction for Multigigabit Networks",
booktitle="Proceedings of the 2009 IEEE Symphosium on Design and Diagnostics of Electronic Circuits and Systems",
year="2009",
pages="96--101",
publisher="IEEE Computer Society",
address="Liberec",
isbn="978-1-4244-3339-1"
}