Result Details

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

KAŠTIL, J.; STRAKA, M.; MIČULKA, L.; KOTÁSEK, Z. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 250-257. ISBN: 978-0-7695-4798-5.
Type
conference paper
Language
English
Authors
Kaštil Jan, Ing., Ph.D., DIFS (FIT), DCSY (FIT)
Straka Martin, Ing., Ph.D., DIFS (FIT), DCGM (FIT)
Mičulka Lukáš, Ing., Ph.D., DCGM (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on redundancy of functional units associated with a concurrent error detection technique and it uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture the Markov dependability models are created and it is demonstrated how the reliability and availability parameters are derived from this model for different configurations of architectures and faulty modules. The reliability analysis results are shown.

Keywords

dependability, reliability, model, FPGA, fault tolerant system, architecture, reconfiguration

Published
2012
Pages
250–257
Proceedings
15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Conference
15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
ISBN
978-0-7695-4798-5
Publisher
IEEE Computer Society
Place
Cesme-Izmir
BibTeX 
@inproceedings{BUT96980,
  author="Jan {Kaštil} and Martin {Straka} and Lukáš {Mičulka} and Zdeněk {Kotásek}",
  title="Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA",
  booktitle="15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  year="2012",
  pages="250--257",
  publisher="IEEE Computer Society",
  address="Cesme-Izmir",
  isbn="978-0-7695-4798-5",
  url="https://www.fit.vut.cz/research/publication/10037/"
}
Files
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
National Support for Project Reduced Certification Costs Using Trusted Multi-core Platforms, MŠMT, Společné technologické iniciativy, 7H10013, start: 2010-04-01, end: 2013-03-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
Back to top