Detail výsledku
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA
Straka Martin, Ing., Ph.D., UIFS (FIT), UPGM (FIT)
Mičulka Lukáš, Ing., Ph.D., UPGM (FIT)
Kotásek Zdeněk, doc. Ing., CSc., UPSY (FIT), UTKO (FEKT)
In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on redundancy of functional units associated with a concurrent error detection technique and it uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture the Markov dependability models are created and it is demonstrated how the reliability and availability parameters are derived from this model for different configurations of architectures and faulty modules. The reliability analysis results are shown.
dependability, reliability, model, FPGA, fault tolerant system, architecture, reconfiguration
@inproceedings{BUT96980,
author="Jan {Kaštil} and Martin {Straka} and Lukáš {Mičulka} and Zdeněk {Kotásek}",
title="Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA",
booktitle="15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
year="2012",
pages="250--257",
publisher="IEEE Computer Society",
address="Cesme-Izmir",
isbn="978-0-7695-4798-5",
url="https://www.fit.vut.cz/research/publication/10037/"
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