Course details

Functional Verification of Digital Systems

FVS Acad. year 2023/2024 Summer semester 5 credits

Course is not open in this year

Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping. Validation.

Guarantor

Course coordinator

Language of instruction

Czech

Completion

Examination (written+oral)

Time span

  • 26 hrs lectures
  • 8 hrs laboratories
  • 18 hrs projects

Assessment points

  • 60 pts final exam
  • 20 pts labs
  • 20 pts projects
  • 5 pts homework

Department

Lecturer

Learning objectives

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.


A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to UVM verification methodology.

Why is the course taught

Students gain knowledge which is very valuable for their future employement, as verification is an important part of hardware development.

Prerequisite knowledge and skills

Digital system design, basic programming skills.

Study literature

  • Přednáškové materiály v elektronické formě.
  • Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
  • Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
  • Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
  • Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.

Fundamental literature

  • * Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175. * Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217 * Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141. * Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418. 

Syllabus of lectures

  1. Motivation and history of verification
  2. Simulation-based verification
  3. Functional verification: introduction
  4. Verification methodologies
  5. Self-checking mechanisms + LAB 1
  6. SystemVerilog: data types, stimuli generation + LAB 2
  7. Coverage analysis + LAB 3
  8. Assertions
  9. Assertions-based verification + LAB 4
  10. Register Abstraction Layer
  11. Invited lecture
  12. Validation
  13. Verification trends

Syllabus of laboratory exercises

  1. Reference model implementation.
  2. Verification tests implementation.
  3. Coverage-driven verification.
  4. Assertions-based verification.

Syllabus - others, projects and individual work of students

Design and implementation of verification environment for a selected digital systém.

Progress assessment

Labs and project in due dates.

Exam prerequisites

Requirements for class accreditation are not defined.

Course inclusion in study plans

Back to top