Thesis Details
Vizualizace činnosti vyrovnávacích pamětí procesoru
The goal of this work is to design and implement CPU cache simulator. In today's computers there is a difference of orders of magnitude between performance of CPUs and the main memory and thus it is necessary to use caches as an interlayer. The simulator will demonstrate effect of caches on different algorithms and problems that can occur if they are used inappropriately. For ease of use the simulator is implemented as a web application using framework Vue.js. User can enter assembly code and then execute it on several different types of caches. The application visualizes data flow between main memory and cache. Several sample programs were also created, which demonstrate various properties and problems of caches. With this application it is possible to clearly show significance of cache memory.
cache, cache memory, CPU cache, memory hierarchy, simulator, cache simulator, visualization, cache visualization, assembler, web appliacation, JavaScript front-end framework, Vue.js
Bidlo Michal, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Hliněná Dana, doc. RNDr., Ph.D. (DMAT FEEC BUT), člen
Musil Miloš, Ing., Ph.D. (DIFS FIT BUT), člen
Rogalewicz Adam, doc. Mgr., Ph.D. (DITS FIT BUT), člen
@bachelorsthesis{FITBT24948, author = "Daniel Pe\v{r}ina", type = "Bachelor's thesis", title = "Vizualizace \v{c}innosti vyrovn\'{a}vac\'{i}ch pam\v{e}t\'{i} procesoru", school = "Brno University of Technology, Faculty of Information Technology", year = 2022, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/24948/" }