Result Details

Fast Just-In-Time Translated Simulation for ASIP Design

PŘIKRYL, Z.; KŘOUSTEK, J.; HRUŠKA, T.; KOLÁŘ, D. Fast Just-In-Time Translated Simulation for ASIP Design. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011. p. 279-282. ISBN: 978-1-4244-9753-9.
Type
conference paper
Language
English
Authors
Přikryl Zdeněk, Ing., Ph.D., DIFS (FIT)
Křoustek Jakub, Ing., Ph.D., DIFS (FIT)
Hruška Tomáš, prof. Ing., CSc., DIFS (FIT)
Kolář Dušan, doc. Dr. Ing., DIFS (FIT)
Abstract

Thefast and accurate processor simulator is an essential tool foreffective design of modern high-performance application-specificinstruction set processors. The nowadays trend of ASIP design isfocused on automatic simulator generation based on a processordescription in an architecture description language. The simulator isused for testing and validation of designed processor or targetapplication. Furthermore, the simulator can produce the profilinginformation. This information can aid design space exploration andthe processor and target application optimization. In this paper, wepresent the concept of automatically generated just-in-timetranslated simulator with the profiling capabilities. This simulatoris very fast, and it is generated in a short time. It can be evenused for simulation of special applications, such as applicationswith self-modifying code or applications for systems with externalmemories. The experimental results can be found at the end of thepaper.

Keywords

Architecturedescription languages, simulation, testing, application-specificinstruction set processors

Published
2011
Pages
279–282
Proceedings
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus
DOI
10.1109/DDECS.2011.5783094
UT WoS
000312912900055
BibTeX 
@inproceedings{BUT76314,
  author="Zdeněk {Přikryl} and Jakub {Křoustek} and Tomáš {Hruška} and Dušan {Kolář}",
  title="Fast Just-In-Time Translated Simulation for ASIP Design",
  booktitle="14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2011",
  pages="279--282",
  publisher="IEEE Computer Society",
  address="Cottbus",
  doi="10.1109/DDECS.2011.5783094",
  isbn="978-1-4244-9753-9"
}
Projects
Advanced recognition and presentation of multimedia data, BUT, Vnitřní projekty VUT, FIT-S-11-2, start: 2011-01-01, end: 2013-12-31, completed
Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems, GACR, Doktorské granty, GD102/09/H042, start: 2009-01-30, end: 2012-12-31, completed
National Support for Project Smart Multicore Embedded SYstems, MŠMT, Společné technologické iniciativy, 7H10014, start: 2010-02-01, end: 2013-01-31, running
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
System for Programming and Realization of Embedded Systems, MPO, TIP, FR-TI1/038, start: 2009-07-01, end: 2013-06-30, completed
System for Support of Platform Independent Malware Analysis in Executable Files, TAČR, Program aplikovaného výzkumu a experimentálního vývoje ALFA, TA01010667, start: 2011-01-01, end: 2013-12-31, completed
Research groups
Hardware-Software Codesign research group (RG LISSOM)
Departments
Department of Information Systems (DIFS)
Back to top