Thesis Details
Use of verification for testing fault-tolerance in FPGA-based system
Fault tolerance is one of the most commonly used techniques to eliminate the effect of faults on digital systems and increase their reliability. This work presents a platform for testing such fault tolerance techniques targeted to FPGA-based systems. The platform uses the principles of functional verification, while the experimental electronic controller is moved to the FPGA, which allows the use of fault injection directly into the FPGA. The platform makes it possible to use the electro-mechanical application as an experimental system and allows to monitor the effect of faults on both the electronic controller and the behavior of controlled mechanical part. This work presents experiments with two experimental systems - robot for finding a path through a maze and an electronic lock. The platform is designed to allow the use of any experimental system with an electronic control unit implemented in the FPGA
FPGA, fault tolerance, reliability, fault injection, functional verification, electro-mechanical system.
@phdthesis{FITPT885,
author = "Jakub Podiv\'{i}nsk\'{y}",
type = "Ph.D. thesis",
title = "Use of verification for testing fault-tolerance in FPGA-based system",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2021,
location = "Brno, CZ",
language = "english",
url = "https://www.fit.vut.cz/study/phd-thesis/885/"
}