Thesis Details

Graphical Simulator of Superscalar Processors

Master's Thesis Student: Vávra Jan Academic Year: 2020/2021 Supervisor: Jaroš Jiří, doc. Ing., Ph.D.
Czech title
Grafický simulátor superskalárních procesorů
Language
English
Abstract

The focus of this thesis is implementation of the superscalar simulator. The implementation follows research of existing simulators and tries to implement missing features from them. Simulator uses RISC-V instruction set architecture, but architecture can be swapped for any RISC instruction set. Simulator implements deterministic branch prediction. Parts of the simulation can be configured. The simulator application also contains a text editor for inputting source code.

Keywords

simulator, superscalar, processor, interactive, Java, OOP, RISC-V, branch prediction, Gshare, Tomasulo algorithm, data hazards, load bypassing, load forwarding

Department
Degree Programme
Information Technology and Artificial Intelligence, Specialization Embedded Systems
Files
Status
defended, grade A
Date
22 June 2021
Reviewer
Committee
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY FIT BUT), předseda
Bidlo Michal, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Češka Milan, prof. RNDr., CSc. (DITS FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Martínek Tomáš, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Orság Filip, Ing., Ph.D. (DITS FIT BUT), člen
Citation
VÁVRA, Jan. Graphical Simulator of Superscalar Processors. Brno, 2021. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2021-06-22. Supervised by Jaroš Jiří. Available from: https://www.fit.vut.cz/study/thesis/21991/
BibTeX
@mastersthesis{FITMT21991,
    author = "Jan V\'{a}vra",
    type = "Master's thesis",
    title = "Graphical Simulator of Superscalar Processors",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2021,
    location = "Brno, CZ",
    language = "english",
    url = "https://www.fit.vut.cz/study/thesis/21991/"
}
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