Publications
-
2025
BOSIO, A.; BERNARDI, P.; TRAIOLA, M.; MRÁZEK, V. 28th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Lyon: Institute of Electrical and Electronics Engineers, 2025. ISBN: 979-8-3315-2801-0. Detail
HURTA, M.; OVESNÁ, A.; MRÁZEK, V.; SEKANINA, L. Multi-Objective Evolutionary Design of Explainable EEG Classifier. Genetic Programming, 28th European Conference, EuroGP 2025. Lecture Notes in Computer Science. Terst: Springer Nature Switzerland AG, 2025.
p. 52-67. ISBN: 978-3-031-89990-4. DetailMASÁR, F.; MRÁZEK, V.; SEKANINA, L. Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. In 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lyon: Institute of Electrical and Electronics Engineers, 2025.
p. 1-2. ISBN: 978-3-9826741-0-0. DetailPIŇOS, M.; KLHŮFEK, J.; MRÁZEK, V.; SEKANINA, L. Inference Energy Analysis in Context of Hardware-Aware NAS. In 2025 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Lyon: Institute of Electrical and Electronics Engineers, 2025.
p. 161-164. ISBN: 979-8-3315-2801-0. Detail -
2024
DENIZIAK, S.; SITEK, P.; JENIHHIN, M.; STEININGER, A.; SCHÖLZEL, M.; MRÁZEK, V. 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Kliece: Institute of Electrical and Electronics Engineers, 2024. ISBN: 979-8-3503-5934-3. Detail
KLHŮFEK, J.; ŠAFÁŘ, M.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS). Kielce: Institute of Electrical and Electronics Engineers, 2024.
p. 1-6. ISBN: 979-8-3503-5934-3. DetailMRÁZEK, V.; KOKKINIS, A.; PAPANIKOLAOU, P.; VAŠÍČEK, Z.; SIOZIOS, K.; TZIMPRAGOS, G.; TAHOORI, M.; ZERVAKIS, G. Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. 2024 IEEE/ACM International Conference on Computer Aided Design (ICCAD). New York: Association for Computing Machinery, 2024.
p. 1-9. ISBN: 979-8-4007-1077-3. DetailPIŇOS, M.; SEKANINA, L.; MRÁZEK, V. ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. In 2024 The International Joint Conference on Neural Networks (IJCNN). Yokohama: Institute of Electrical and Electronics Engineers, 2024.
p. 1-8. ISBN: 979-8-3503-5931-2. DetailŠÍMA, J.; VIDNEROVÁ, P.; MRÁZEK, V. Energy Complexity of Convolutional Neural Networks. NEURAL COMPUTATION, 2024, vol. 36, no. 8,
p. 1601-1625. ISSN: 0899-7667. DetailVAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024.
p. 1-6. ISBN: 979-8-3503-4859-0. Detail -
2023
HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. Multi-objective Design of Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. Evo* 2023 -- Late-Breaking Abstracts Volume. Brno: 2023. Detail
HURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). Antwerp: Institute of Electrical and Electronics Engineers, 2023.
p. 1-2. ISBN: 978-3-9819263-7-8. DetailHURTA, M.; MRÁZEK, V.; DRAHOŠOVÁ, M.; SEKANINA, L. MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallinn: Institute of Electrical and Electronics Engineers, 2023.
p. 155-160. ISBN: 979-8-3503-3277-3. DetailMARCHISIO, A.; BUSSOLINO, B.; COLUCCI, A.; MRÁZEK, V.; HANIF, M.; MARTINA, M.; MASERA, G.; SHAFIQUE, M. Hardware and Software Optimizations for Capsule Networks. In Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing. Cham: Springer Nature Switzerland AG, 2023.
p. 303-328. ISBN: 978-3-031-39932-9. DetailMRÁZEK, V. Approximation of Hardware Accelerators driven by Machine-Learning Models. In Proceedings of International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '23). Tallinn: Institute of Electrical and Electronics Engineers, 2023.
p. 91-92. ISBN: 979-8-3503-3277-3. DetailMRÁZEK, V.; JAWED, S.; ARIF, M.; MALIK, A. Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. In GECCO 2023 - Proceedings of the 2023 Genetic and Evolutionary Computation Conference. Lisbon: Association for Computing Machinery, 2023.
p. 1427-1435. ISBN: 979-8-4007-0119-1. DetailPIŇOS, M.; MRÁZEK, V.; SEKANINA, L. Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. In 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Talinn: Institute of Electrical and Electronics Engineers, 2023.
p. 45-50. ISBN: 979-8-3503-3277-3. DetailPIŇOS, M.; MRÁZEK, V.; VAVERKA, F.; VAŠÍČEK, Z.; SEKANINA, L. Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, vol. 13, no. 1,
p. 212-224. ISSN: 2156-3357. DetailPRABAKARAN, B.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; SHAFIQUE, M. Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Francisco: Institute of Electrical and Electronics Engineers, 2023.
p. 1-9. ISBN: 979-8-3503-1559-2. DetailSEKANINA, L.; MRÁZEK, V.; PIŇOS, M. Hardware-Aware Evolutionary Approaches to Deep Neural Networks. In Handbook of Evolutionary Machine Learning. Genetic and Evolutionary Computation. Singapore: Springer Nature Singapore, 2023.
p. 367-396. ISBN: 978-981-9938-13-1. DetailŠÍMA, J.; VIDNEROVÁ, P.; MRÁZEK, V. Energy Complexity Model for Convolutional Neural Networks. In Artificial Neural Networks and Machine Learning - ICANN 2023: 32nd International Conference on Artificial Neural Networks. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Heraklion: Springer Nature Switzerland AG, 2023.
p. 186-198. ISBN: 978-3-031-44203-2. Detail -
2022
SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Inexact Arithmetic Operators. In Approximate Computing Techniques. Cham: Springer International Publishing, 2022.
p. 81-107. ISBN: 978-3-030-94704-0. Detail -
2018
ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. ADAC: Automated Design of Approximate Circuits. In Proceedings of 30th International Conference on Computer Aided Verification (CAV'18). Oxford, UK: Springer International Publishing, 2018.
p. 612-620. ISBN: 978-3-319-96145-3. DetailMRÁZEK, V.; SÝS, M.; VAŠÍČEK, Z.; SEKANINA, L.; MATYÁŠ, V. Evolving Boolean Functions for Fast and Efficient Randomness Testing. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '18). Kyoto: Association for Computing Machinery, 2018.
p. 1302-1309. ISBN: 978-1-4503-5618-3. DetailMRÁZEK, V.; VAŠÍČEK, Z. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018.
p. 294-295. ISBN: 978-1-4503-5764-7. DetailMRÁZEK, V.; VAŠÍČEK, Z.; HRBÁČEK, R. Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Computers and Digital Techniques, 2018, vol. 2018, no. 4,
p. 139-149. ISSN: 1751-8601. DetailMRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. In Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh: Institute of Electrical and Electronics Engineers, 2018.
p. 264-271. ISBN: 978-1-5386-7753-7. DetailMRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; JIANG, H.; HAN, J. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. on VLSI Systems., 2018, vol. 26, no. 11,
p. 2572-2576. ISSN: 1063-8210. DetailSEKANINA, L.; MRÁZEK, V.; VAŠÍČEK, Z. Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. In 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Bordeaux: IEEE Circuits and Systems Society, 2018.
p. 377-380. ISBN: 978-1-5386-9562-3. Detail -
2017
ČEŠKA, M.; MATYÁŠ, J.; MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; VOJNAR, T. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017.
p. 416-423. ISBN: 978-1-5386-3093-8. DetailMRÁZEK, V.; HRBÁČEK, R.; VAŠÍČEK, Z.; SEKANINA, L. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017.
p. 258-261. ISBN: 978-3-9815370-9-3. DetailMRÁZEK, V.; VAŠÍČEK, Z. Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming. In GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference. Berlin: Association for Computing Machinery, 2017.
p. 1849-1856. ISBN: 978-1-4503-4939-0. DetailSEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Approximate Circuits in Low-Power Image and Video Processing: The Approximate Median Filter. Radioengineering, 2017, vol. 26, no. 3,
p. 623-632. ISSN: 1210-2512. DetailSHAFIQUE, M.; HAFIZ, R.; JAVED, M.; ABBAS, S.; SEKANINA, L.; VAŠÍČEK, Z.; MRÁZEK, V. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017.
p. 627-632. ISBN: 978-1-5090-6762-6. DetailVAŠÍČEK, Z.; MRÁZEK, V. Trading between Quality and Non-functional Properties of Median Filter in Embedded Systems. Genetic Programming and Evolvable Machines, 2017, vol. 18, no. 1,
p. 45-82. ISSN: 1389-2576. DetailVAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Towards Low Power Approximate DCT Architecture for HEVC Standard. In Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017.
p. 1576-1581. ISBN: 978-3-9815370-9-3. Detail -
2016
HRBÁČEK, R.; MRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Approximate Circuits by Means of Multi-Objective Evolutionary Algorithms. In Proceedings of the 11th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Istanbul: Istanbul Sehir University, 2016.
p. 239-244. ISBN: 978-1-5090-0335-8. DetailMRÁZEK, V. Evoluční snižování příkonu: Od obvodů na úrovni tranzistorů po neuronové sítě na čipu. Počítačové architektury a diagnostika PAD 2016. Bořetice: Fakulta informačních technologií VUT v Brně, 2016.
s. 61-64. ISBN: 978-80-214-5376-0. DetailMRÁZEK, V.; SARWAR, S.; SEKANINA, L.; VAŠÍČEK, Z.; ROY, K. Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. Austin, TX: Association for Computing Machinery, 2016.
p. 811-817. ISBN: 978-1-4503-4466-1. DetailMRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on. Bremen: Institute of Electrical and Electronics Engineers, 2016.
p. 221-228. ISBN: 978-1-5090-0733-2. DetailNEVORAL, J.; RŮŽIČKA, R.; MRÁZEK, V. Evolutionary Design of Polymorphic Gates Using Ambipolar Transistors. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016.
p. 1-8. ISBN: 978-1-5090-4240-1. DetailVAŠÍČEK, Z.; MRÁZEK, V.; SEKANINA, L. Evolutionary Functional Approximation of Circuits Implemented into FPGAs. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016.
p. 1-8. ISBN: 978-1-5090-4240-1. Detail -
2015
MRÁZEK, V. Evoluční návrh nízkopříkonových obvodů. Počítačové architektury a diagnostika PAD 2015. Zlín: Fakulta aplikované informatiky, Univerzita Tomáše Bati ve Zlíně, 2015.
s. 1-6. ISBN: 978-80-7454-522-1. DetailMRÁZEK, V.; VAŠÍČEK, Z. Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. In Proceedings of 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing. Porto: Institute of Electrical and Electronics Engineers, 2015.
p. 106-113. ISBN: 978-1-4673-8299-1. DetailMRÁZEK, V.; VAŠÍČEK, Z. Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation. In Genetic Programming, 18th European Conference, EuroGP 2015. LCNS 9025. Berlin: Springer International Publishing, 2015.
p. 66-77. ISBN: 978-3-319-16500-4. DetailMRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L. Evolutionary Approximation of Software for Embedded Systems: Median Function. In GECCO Companion '15 Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference. ACM. New York: Association for Computing Machinery, 2015.
p. 795-801. ISBN: 978-1-4503-3488-4. Detail -
2014
MRÁZEK, V. Akcelerace evolučního návrhu digitálních obvodů na úrovni tranzistorů s využitím platformy Zynq. Proceedings of the 20th Student Conference, EEICT 2014. Volume 2. Brno: Vysoké učení technické v Brně, 2014.
s. 229-231. ISBN: 978-80-214-4923-7. DetailMRÁZEK, V.; VAŠÍČEK, Z. Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform. In 2014 IEEE International Conference on Evolvable Systems Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2014.
p. 9-16. ISBN: 978-1-4799-4480-4. Detail