Course details

Advanced Digital Systems

PCS Acad. year 2013/2014 Winter semester 5 credits

Current academic year

Combinatorial and sequential logic design techniques, algorithms, and tools review. Review of digital design target technologies (ASIC, FPGA). Algorithms for minimization of digital circuits. Advanced synthesis techniques (pipelining, retiming). Constraint conditions. High-level synthesis (scheduling, allocation, binding). High-level synthesis (loop synthesis). Digital design using CatapultC environment (basic statements in C/C++). Digital design using CatapultC environment (loops, memory access). Low power design methodologies.
Reconfigurable computing. Verification of digital circuits (OVM methodology).

Guarantor

Fučík Otto, doc. Dr. Ing. (DCSY)

Language of instruction

Czech

Completion

Examination

Time span

  • 26 hrs lectures
  • 10 hrs pc labs
  • 16 hrs projects

Department

Department of Computer Systems (UPSY)

Subject specific learning outcomes and competences

The students are able to design complex constrained digital systems using contemporary design techniques, high-level description language (C/C++) and professional CAD tools (CatapultC).

Learning objectives

To give the students the knowledge of advanced digital systems design including hardware description languages, professional CAD tools, techniques for constrained design, and PLD technology.

Prerequisite knowledge and skills

Digital system design, basic programming skills.

Study literature

  • Přednáškové materiály v elektronické podobě.
  • Khatri S. P., Gulati K. (eds.): Advanced Techniques in Logic Synthesis, Optimizations and Applications, ISBN 978-1-4419-7517-1, 2011
  • Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

Fundamental literature

  • Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008

Syllabus of lectures

  • Combinational and sequential logic design techniques, algorithms, and tools review.
  • Structured design concept. Design strategies. Design decomposition. Design tools.
  • Introduction to VHDL
  • Basic features of VHDL. Simulation and synthesis.
  • Basic VHDL modeling techniques.
  • Algorithmic level design.
  • Register Level Design.
  • HDL-based design techniques. Constrained design.
  • ASIC and PLD design process. Fast prototyping.
  • Modeling for synthesis.
  • Top-down design methodology in VHDL.
  • Design case study.
  • Design automation algorithms. HW/SW co-design.

Syllabus of computer exercises

  • Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
  • Combinational logic circuits modeling and simulation using VHDL.
  • Sequential logic circuits modeling and simulation using VHDL.
  • A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.

Progress assessment

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Requirements for class accreditation are not defined.

Teaching methods and criteria

The course uses teaching methods in form of Lecture - 2 teaching hours per week, Computer exercise - 1 teaching hour per week, Projects - 1 teaching hour per week.

Controlled instruction

Written mid-term exam and project in due dates.

Course inclusion in study plans

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