Course details

Diagnosis and Safe Systems

DIA Acad. year 2004/2005 Summer semester 6 credits

Current academic year

Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.

Guarantor

Drábek Vladimír, doc. Ing., CSc. (DCSY)

Language of instruction

Czech

Completion

Examination

Time span

  • 39 hrs lectures
  • 10 hrs exercises
  • 6 hrs laboratories
  • 10 hrs projects

Department

Department of Computer Systems (UPSY)

Subject specific learning outcomes and competences

Basic approaches to test generation and design for testability.

Learning objectives

To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.

Prerequisite knowledge and skills

There are no prerequisites

Syllabus of lectures

  • Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  • Test generation approaches.
  • Funkctional tests.
  • Sequential circuit testing.
  • Test generation at RTL level.
  • Random and pseudorandom test generation.
  • Location sequences.
  • Fault dictionaries.
  • Diagnostic data compression.
  • Design for testability.
  • Built-in diagnosis.
  • Memory testing.
  • Processor and wiring testing.
  • Fail-safe circuits.
  • Fault-tolerance priciples.
  • Diagnostic equipment.

Syllabus of numerical exercises

  • Fault models for TTL, CMOS, PLA and bridge faults.
  • Test generation approaches.
  • Functional tests.
  • Sequential circuit testing.
  • RTL-level test generation.
  • Random and pseudorandom test generation.

Syllabus of laboratory exercises

  • Adder with built-in self test.
  • Linear feedback shift register.
  • Linear cellular automata.
  • Boundary scan testing.
  • Memory testing.

Progress assessment

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Pass a mid-term exam and a project.

Controlled instruction

Mid-term exam and a project.

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