Thesis Details
Transformace popisného jazyka mikroprocesoru do jazyka pro popis hardware
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
transformation, processor, microprocessor, embedded system, ISAC language, project Lissom, VHDL language, processor's templates, process graph, hardware/software co-design
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Šafařík Jiří, prof. Ing., CSc. (WBU in Pilsen), člen
Švéda Miroslav, prof. Ing., CSc. (DIFS FIT BUT), člen
Vojnar Tomáš, prof. Ing., Ph.D. (DITS FIT BUT), člen
Zbořil František, doc. Ing., Ph.D. (DITS FIT BUT), člen
@mastersthesis{FITMT4747, author = "Tom\'{a}\v{s} Novotn\'{y}", type = "Master's thesis", title = "Transformace popisn\'{e}ho jazyka mikroprocesoru do jazyka pro popis hardware", school = "Brno University of Technology, Faculty of Information Technology", year = 2007, location = "Brno, CZ", language = "czech", url = "https://www.fit.vut.cz/study/thesis/4747/" }