Thesis Details

Systém interních sběrnic pro čipy s technologií FPGA

Master's Thesis Student: Málek Tomáš Academic Year: 2007/2008 Supervisor: Martínek Tomáš, doc. Ing., Ph.D.
English title
System of Internal Buses for Chips with FPGA Technology
Language
Czech
Abstract

This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.

Keywords

Bus, interconnection system, PCI, PCI-X, PCI Express, FPGA, VHDL

Department
Department of Computer Systems FIT BUT
Degree Programme
Information Technology, Field of Study Computer Systems and Networks
Files
Status
defended, grade A
Date
18 June 2008
Reviewer
Kořenek Jan, doc. Ing., Ph.D.
Committee
Dvořák Václav, prof. Ing., DrSc. (DCSY FIT BUT), předseda
Drábek Vladimír, doc. Ing., CSc. (DCSY FIT BUT), člen
Herout Adam, prof. Ing., Ph.D. (DCGM FIT BUT), člen
Janoušek Vladimír, doc. Ing., Ph.D. (DITS FIT BUT), člen
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT), člen
Krejčíček Jaromír, prof. Ing., CSc. (UNOB), člen
Citation
MÁLEK, Tomáš. Systém interních sběrnic pro čipy s technologií FPGA. Brno, 2008. Master's Thesis. Brno University of Technology, Faculty of Information Technology. 2008-06-18. Supervised by Martínek Tomáš. Available from: https://www.fit.vut.cz/study/thesis/6598/
BibTeX 
@mastersthesis{FITMT6598,
    author = "Tom\'{a}\v{s} M\'{a}lek",
    type = "Master's thesis",
    title = "Syst\'{e}m intern\'{i}ch sb\v{e}rnic pro \v{c}ipy s technologi\'{i} FPGA",
    school = "Brno University of Technology, Faculty of Information Technology",
    year = 2008,
    location = "Brno, CZ",
    language = "czech",
    url = "https://www.fit.vut.cz/study/thesis/6598/"
}

Theses

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