Publications
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2021
FUKAČ, T.; MATOUŠEK, J.; KOŘENEK, J.; KEKELY, L. Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. In 2021 International Conference on Field-Programmable Technology, ICFPT 2021. Auckland: Institute of Electrical and Electronics Engineers, 2021.
p. 185-193. ISBN: 978-1-6654-2010-5. Detail -
2020
KEKELY, L.; CABAL, J.; PUŠ, V.; KOŘENEK, J. Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: IEEE Computer Society, 2020.
p. 49-56. ISBN: 978-1-7281-9535-3. DetailKEKELY, M.; KEKELY, L.; KOŘENEK, J. General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocessors and Microsystems, 2020, vol. 73, no. 3,
p. 1-12. ISSN: 0141-9331. DetailKOŘENEK, J.; KORČEK, P.; KEKELY, L. Akcelerace analýzy síťového provozu. DSM Data Security Management, 2020, roč. 24, č. 4,
s. 30-34. ISSN: 1211-8737. Detail -
2019
KEKELY, L.; CABAL, J.; KOŘENEK, J. Effective FPGA Architecture for General CRC. In Architecture of Computing Systems - ARCS 2019. Neuvedeno: Springer International Publishing, 2019.
p. 211-223. ISBN: 978-3-030-18655-5. DetailKUČERA, J.; KEKELY, L.; PIECEK, A.; KOŘENEK, J. General IDS Acceleration for High-Speed Networks. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Orlando: Institute of Electrical and Electronics Engineers, 2019.
p. 366-373. ISBN: 978-1-5386-8477-1. Detail -
2018
CABAL, J.; BENÁČEK, P.; KEKELY, L.; KEKELY, M.; PUŠ, V.; KOŘENEK, J. Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York: Association for Computing Machinery, 2018.
p. 249-258. ISBN: 978-1-4503-5614-5. DetailKEKELY, L.; CABAL, J.; KOŘENEK, J. High-Speed Computation of CRC Codes for FPGAs. In Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018). Naha: IEEE Computer Society, 2018.
p. 237-240. ISBN: 978-1-7281-0214-6. DetailKEKELY, M.; KEKELY, L.; KOŘENEK, J. Memory Aware Packet Matching Architecture for High-Speed Networks. In Proceedings of the 21st Euromicro Conference on Digital Systems Design. Praha: IEEE Computer Society, 2018.
p. 1-8. ISBN: 978-1-5386-7376-8. DetailKUČERA, J.; KEKELY, L.; PUŠ, V.; PIECEK, A.; KOŘENEK, J. Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks. In Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018.
p. 177-178. ISBN: 978-1-4503-5902-3. Detail -
2015
KEKELY, L.; KUČERA, J.; PUŠ, V.; KOŘENEK, J.; VASILAKOS, A. Software Defined Monitoring of Application Protocols. IEEE TRANSACTIONS ON COMPUTERS, 2015, vol. 65, no. 2,
p. 615-626. ISSN: 0018-9340. DetailKEKELY, L.; VRÁNA, R.; ŽÁDNÍK, M. Report z testování prototypu 100Gb/s sondy pro zákonné odposlechy. FIT-TR-2015-001, Brno: Fakulta informačních technologií VUT v Brně, 2015.
s. 0-0. DetailŽÁDNÍK, M.; KEKELY, L.; VRÁNA, R.; HOLKOVIČ, M.; FRANKOVÁ, B. Dokumentace pro sestavení a zprovoznění prototypu hardwarově akcelerované sondy pro legální odposlechy. Brno: Fakulta informačních technologií VUT v Brně, 2015.
s. 0-0. Detail -
2014
KEKELY, L. Software Defined Monitoring: Nový prístup k monitorovaniu vysokorýchlostných počítačových sietí. Počítačové architektury a diagnostika 2014. Liberec: Liberec University of Technology, 2014.
s. 74-79. ISBN: 978-80-7494-027-9. DetailKEKELY, L.; PUŠ, V.; BENÁČEK, P.; KOŘENEK, J. Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014). Munich: IEEE Circuits and Systems Society, 2014.
p. 264-267. ISBN: 978-3-00-044645-0. DetailKEKELY, L.; PUŠ, V.; KOŘENEK, J. Software Defined Monitoring of Application Protocols. In Proceedings of IEEE INFOCOM 2014 - IEEE Conference on Computer Communications. Toronto: IEEE Computer Society, 2014.
p. 1725-1733. ISBN: 978-1-4799-3360-0. DetailKEKELY, L.; ŽÁDNÍK, M.; MATOUŠEK, J.; KOŘENEK, J. Fast Lookup for Dynamic Packet Filtering in FPGA. In Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014. Warszawa: IEEE Computer Society, 2014.
p. 219-222. ISBN: 978-1-4799-4558-0. DetailPUŠ, V.; KEKELY, L.; KOŘENEK, J. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014.
p. 189-194. ISBN: 978-1-4799-4558-0. DetailZÁVODNÍK, T.; KEKELY, L.; PUŠ, V. CRC based hashing in FPGA using DSP blocks. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014.
p. 179-182. ISBN: 978-1-4799-4558-0. Detail -
2012
KEKELY, L.; PUŠ, V.; KOŘENEK, J. Low-Latency Modular Packet Header Parser for FPGA. ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012.
p. 77-78. ISBN: 978-1-4503-1685-9. DetailŽÁDNÍK, M.; KEKELY, L. Hardwarově akcelerovaná sonda pro legální odposlechy. FIT-TR-2012-005, Brno: Fakulta informačních technologií VUT v Brně, 2012.
s. 0-0. Detail