Faculty of Information Technology, BUT

Doc. Ing.

Zdeněk Kotásek

CSc.

Deputy Head of Department

+420 54114-1223
kotasek@fit.vut.cz
Office L336

Publications

  • 2019

    SZURMAN Karel and KOTÁSEK Zdeněk. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 32-35. ISBN 978-1-72811-755-3.
    Detail

    KRČMA Martin and KOTÁSEK Zdeněk. Detecting hard synapses faults in artificial neural networks. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019, pp. 1-6. ISBN 978-1-72811-755-3.
    Detail

    PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 97-100. ISBN 978-1-72811-755-3.
    Detail

    SZURMAN Karel and KOTÁSEK Zdeněk. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy, 2019.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš and KOTÁSEK Zdeněk. Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. In: Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019, pp. 597-600. ISBN 978-1-72812-861-0.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In: 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019, pp. 93-96. ISBN 978-1-72811-755-3.
    Detail

    SZURMAN Karel and KOTÁSEK Zdeněk. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In: 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019, pp. 136-140. ISBN 978-1-72810-072-2.
    Detail

    ČEKAN Ondřej, PODIVÍNSKÝ Jakub, LOJDA Jakub, PÁNEK Richard, KRČMA Martin and KOTÁSEK Zdeněk. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In: Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019, pp. 506-513. ISBN 978-1-72812-861-0.
    Detail

  • 2018

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, KRČMA Martin, BURGET Radek, HRUŠKA Tomáš and KOTÁSEK Zdeněk. A Framework for Optimizing a Processor to Selected Application. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 564-574. ISBN 978-1-5386-5709-6.
    Detail

    PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 63-69. ISBN 978-1-5386-5709-6.
    Detail

    LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 5-8. ISBN 978-80-261-0814-6.
    Detail

    PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej and KOTÁSEK Zdeněk. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 229-236. ISBN 978-1-5386-7376-8.
    Detail

    LOJDA Jakub and KOTÁSEK Zdeněk. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018, pp. 31-32. ISBN 978-80-01-06456-6.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 80-86. ISBN 978-1-5386-5709-6.
    Detail

    PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, pp. 9-12.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 244-251. ISBN 978-1-5386-7376-8.
    Detail

    ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 331-336. ISBN 978-1-5386-5709-6.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In: 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018, pp. 1-4. ISBN 978-1-5386-7311-9.
    Detail

    PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018, pp. 129-134. ISBN 978-1-5386-5709-6.
    Detail

    ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Program Generation Through a Probabilistic Constrained Grammar. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 214-220. ISBN 978-1-5386-7376-8.
    Detail

    ČEKAN Ondřej and KOTÁSEK Zdeněk. Random Test Generation Through a Probabilistic Constrained Grammar. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, pp. 5-8.
    Detail

    PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018, pp. 33-34. ISBN 978-80-01-06456-6.
    Detail

  • 2017

    LOJDA Jakub and KOTÁSEK Zdeněk. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 79-80. ISBN 978-80-01-06178-7.
    Detail

    ČEKAN Ondřej and KOTÁSEK Zdeněk. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In: Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: TU Vienna, 2017, pp. 356-359. ISBN 978-1-5386-2146-2.
    Detail

    KRČMA Martin and KOTÁSEK Zdeněk. Approximation accuracy of different FPNN types. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
    Detail

    LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 59-62. ISBN 978-80-972784-0-3.
    Detail

    KRČMA Martin, KOTÁSEK Zdeněk and LOJDA Jakub. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In: Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017, pp. 125-132. ISBN 978-1-5386-3367-0.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 273-278. ISBN 978-1-5386-3298-7.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub, ZACHARIÁŠOVÁ Marcela, KRČMA Martin and KOTÁSEK Zdeněk. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, vol. 52, no. 5, pp. 145-159. ISSN 0141-9331.
    Detail

    ČEKAN Ondřej and KOTÁSEK Zdeněk. Random Test Stimuli Generation Based on a Probabilistic Grammar. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 43-44. ISBN 978-80-01-06178-7.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 359-364. ISBN 978-1-5386-3298-7.
    Detail

    PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Reliability Analysis and Improvement of FPGA-based Robot Controller. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017, pp. 337-344. ISBN 978-1-5386-2146-2.
    Detail

    SZURMAN Karel and KOTÁSEK Zdeněk. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. In: Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 51-54. ISBN 978-80-972784-0-3.
    Detail

    PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
    Detail

    KRČMA Martin, LOJDA Jakub and KOTÁSEK Zdeněk. Triple Modular Redundancy Used in Field Programmable Neural Networks. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-3298-7.
    Detail

  • 2016

    LOJDA Jakub and KOTÁSEK Zdeněk. A Systematic Approach to the Description of Fault-tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
    Detail

    KRČMA Martin, KOTÁSEK Zdeněk, LOJDA Jakub and KAŠTIL Jan. Comparsion of FPNNs models approximation capabilities and resources utilization. In: Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016, pp. 1-2. ISBN 978-3-902457-46-2.
    Detail

    KRČMA Martin and KOTÁSEK Zdeněk. Fault Tolerant Field Programmable Neural Networks. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub and KOTÁSEK Zdeněk. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, pp. 293-294. ISBN 978-1-5090-5602-6.
    Detail

    LOJDA Jakub, PODIVÍNSKÝ Jakub, KRČMA Martin and KOTÁSEK Zdeněk. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, pp. 301-302. ISBN 978-1-5090-5602-6.
    Detail

    KRČMA Martin, KOTÁSEK Zdeněk and LOJDA Jakub. Implementation of Fault Tolerant Techniques into FPNNs. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, pp. 297-298. ISBN 978-1-5090-5602-6.
    Detail

    ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In: Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016, pp. 295-296. ISBN 978-1-5090-5602-6.
    Detail

    ZACHARIÁŠOVÁ Marcela, BELEŠOVÁ Michaela and KOTÁSEK Zdeněk. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016, pp. 380-387. ISBN 978-1-5090-2816-0.
    Detail

    ČEKAN Ondřej and KOTÁSEK Zdeněk. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016. ISBN 978-80-01-05984-5.
    Detail

    SZURMAN Karel, MIČULKA Lukáš and KOTÁSEK Zdeněk. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
    Detail

    KOTÁSEK Zdeněk and PODIVÍNSKÝ Jakub. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 2016.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub and KOTÁSEK Zdeněk. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In: Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016, pp. 487-494. ISBN 978-1-5090-2817-7.
    Detail

  • 2015

    KEKELYOVÁ Michaela, ZACHARIÁŠOVÁ Marcela, KOTÁSEK Zdeněk and HRUŠKA Tomáš. Application of Evolutionary Algorithms for Optimization of Regression Suites. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, pp. 91-94. ISBN 978-1-4799-6779-7.
    Detail

    ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Automation and Optimization of Coverage-driven Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, pp. 87-94. ISBN 978-1-4673-8035-5.
    Detail

    KRČMA Martin, KOTÁSEK Zdeněk and KAŠTIL Jan. Fault Tolerant Field Programmable Neural Networks. In: 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015, pp. 1-4. ISBN 978-1-4673-6575-8.
    Detail

    PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela, ČEKAN Ondřej and KOTÁSEK Zdeněk. FPGA Prototyping and Accelerated Verification of ASIPs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, pp. 145-148. ISBN 978-1-4799-6779-7.
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    KRČMA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Mapping trained neural networks to FPNNs. In: IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015, pp. 157-160. ISBN 978-1-4799-6779-7.
    Detail

    PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, pp. 13-16.
    Detail

    ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Software Fault Tolerance: the Evaluation by Functional Verification. In: Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015, pp. 284-287. ISBN 978-1-4673-8035-5.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, vol. 39, no. 8, pp. 1215-1230. ISSN 0141-9331.
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    ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Universal Pseudo-random Generation of Assembler Codes for Processors. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015, pp. 70-73.
    Detail

  • 2014

    MATUŠOVÁ Lucie, KAŠTIL Jan and KOTÁSEK Zdeněk. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 326-332. ISBN 978-0-7695-5074-9.
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    PODIVÍNSKÝ Jakub, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Complex Control System for Testing Fault-Tolerance Methodologies. In: Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014, pp. 24-27. ISBN 978-2-11-129175-1.
    Detail

    KOTÁSEK Zdeněk and MIČULKA Lukáš. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 171-174. ISBN 978-0-7695-5074-9.
    Detail

    ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. Solving of Constraint Satisfaction Problem. In: Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014, pp. 291-295. ISBN 978-80-214-4924-4.
    Detail

    SZURMAN Karel, MIČULKA Lukáš and KOTÁSEK Zdeněk. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 704-707. ISBN 978-0-7695-5074-9.
    Detail

    PODIVÍNSKÝ Jakub, ČEKAN Ondřej, ZACHARIÁŠOVÁ Marcela and KOTÁSEK Zdeněk. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In: 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014, pp. 312-319. ISBN 978-1-4799-5793-4.
    Detail

    SZURMAN Karel, MIČULKA Lukáš and KOTÁSEK Zdeněk. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In: 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014, pp. 231-236. ISBN 978-1-4799-6593-9.
    Detail

  • 2013

    ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana and KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013, pp. 35-38. ISBN 978-2-11-129175-1.
    Detail

    ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana and KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013, pp. 275-278. ISBN 978-1-4673-6133-0.
    Detail

    ZACHARIÁŠOVÁ Marcela, PŘIKRYL Zdeněk, HRUŠKA Tomáš and KOTÁSEK Zdeněk. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology, vol. 4, no. 403, pp. 128-138. ISSN 1868-4238.
    Detail

    SZURMAN Karel, KAŠTIL Jan, STRAKA Martin and KOTÁSEK Zdeněk. Fault Tolerant CAN Bus Control System Implemented into FPGA. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013, pp. 289-292. ISBN 978-1-4673-1185-4.
    Detail

    STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk and MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems, vol. 2013, no. 37, pp. 155-173. ISSN 0141-9331.
    Detail

    MIČULKA Lukáš, STRAKA Martin and KOTÁSEK Zdeněk. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. In: 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013, pp. 227-234. ISBN 978-0-7695-5074-9.
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    MIČULKA Lukáš and KOTÁSEK Zdeněk. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. In: The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013, pp. 53-56. ISBN 978-2-11-129175-1.
    Detail

  • 2012

    KAŠTIL Jan, STRAKA Martin, MIČULKA Lukáš and KOTÁSEK Zdeněk. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, pp. 250-257. ISBN 978-0-7695-4798-5.
    Detail

    MIČULKA Lukáš and KOTÁSEK Zdeněk. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012, pp. 20-21. ISBN 978-3-902457-33-2.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. FPGA-based Fault Tolerant Architectures and Their Dependability Analysis. In: MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2012, pp. 1-1.
    Detail

    KOTÁSEK Zdeněk and ŠKARVADA Jaroslav. Low Power Testing. Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012, pp. 395-412. ISBN 978-1-60960-212-3.
    Detail

    KOTÁSEK Zdeněk, BOUDA Jan, ČERNÁ Ivana, SEKANINA Lukáš, VOJNAR Tomáš and ANTOŠ David, ed. Mathematical and Engineering Methods in Computer Science, 7th International Doctoral Workshop, Revised Selected Papers. Lecture Notes in Computer Science, vol. 7119. Berlin: Springer Verlag, 2012. ISBN 978-3-642-25928-9.
    Detail

    KAŠTIL Jan, STRAKA Martin and KOTÁSEK Zdeněk. Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, pp. 1-4.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. In: CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2012, pp. 146-153. ISBN 978-80-8143-049-7.
    Detail

    BARTOŠ Pavel and KOTÁSEK Zdeněk. Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires. In: Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2012, pp. 162-169. ISBN 978-80-8143-049-7.
    Detail

    STRAKA Martin, MIČULKA Lukáš, KAŠTIL Jan and KOTÁSEK Zdeněk. Test Platform for Fault Tolerant Systems Design Qualities Verification. In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012, pp. 336-341. ISBN 978-1-4673-1185-4.
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    ZACHARIÁŠOVÁ Marcela, KAŠTIL Jan and KOTÁSEK Zdeněk. Verification of Fault-tolerant methodologies for FPGA Systems. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, pp. 55-58.
    Detail

  • 2011

    STRAKA Martin, KAŠTIL Jan, NOVOTNÝ Jaroslav and KOTÁSEK Zdeněk. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 397-398. ISBN 978-1-4244-9753-9.
    Detail

    BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011. ISBN 978-80-214-4305-1.
    Detail

    BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 371-374. ISBN 978-1-4244-9753-9.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. In: 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011, pp. 223-230. ISBN 978-0-7695-4494-6.
    Detail

  • 2010

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, pp. 365-372. ISBN 978-0-7695-4171-6.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. In: NORCHIP 2010. Tampere: IEEE Computer Society, 2010, pp. 1-4. ISBN 978-1-4244-8971-8.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Methodology for Design of Highly Dependable Systems in FPGA. In: International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010, pp. 186-193. ISBN 978-80-8086-164-3.
    Detail

    STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, pp. 173-176. ISBN 978-1-4244-6610-8.
    Detail

    ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Faculty of Information Technology BUT, 2010. ISBN 978-80-214-4209-2.
    Detail

    KOTÁSEK Zdeněk, BIDLO Michal and JAROŠ Jiří, ed. Počítačové architektury a diagnostika. Brno: Faculty of Information Technology BUT, 2010. ISBN 978-80-214-4140-8.
    Detail

    KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 364-369. ISBN 978-1-4244-6610-8.
    Detail

    KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010, pp. 644-651. ISBN 978-0-7695-4171-6.
    Detail

    ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274, vol. 2010. Berlin: Springer Verlag, 2010, pp. 181-192. ISBN 978-3-642-15322-8. ISSN 0302-9743.
    Detail

  • 2009

    STRAKA Martin and KOTÁSEK Zdeněk. High Availability Fault Tolerant Architectures Implemented into FPGAs. In: 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009, pp. 108-116. ISBN 978-0-7695-3782-5.
    Detail

    STRAKA Martin and KOTÁSEK Zdeněk. Reliability Models for Fault Tolerant Architectures Based on FPGA. In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2009, pp. 239-239. ISBN 978-80-87342-04-6.
    Detail

    KOTÁSEK Zdeněk and STRAKA Martin. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, vol. 2009, no. 3, pp. 8-15. ISSN 1335-8243.
    Detail

  • 2008

    STRAKA Martin and KOTÁSEK Zdeněk. Design of FPGA-Based Dependable Systems. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008, pp. 240-247. ISBN 978-80-7355-082-0.
    Detail

    STRAKA Martin, KOTÁSEK Zdeněk and WINTER Jan. Digital Systems Architectures Based on On-line Checkers. In: 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008, pp. 81-87. ISBN 978-0-7695-3277-6.
    Detail

    PEČENKA Tomáš, SEKANINA Lukáš and KOTÁSEK Zdeněk. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM Transactions on Design Automation of Electronic Systems, vol. 13, no. 3, pp. 1-21. ISSN 1084-4309.
    Detail

    STRNADEL Josef, PEČENKA Tomáš and KOTÁSEK Zdeněk. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, vol. 27, no. 6, pp. 913-930. ISSN 1335-9150.
    Detail

    SEKANINA Lukáš, STAREČEK Lukáš, KOTÁSEK Zdeněk and GAJDA Zbyšek. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, vol. 4, no. 2, pp. 125-142. ISSN 1548-7199.
    Detail

    ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008, pp. 265-265. ISBN 978-80-7355-082-0.
    Detail

    ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and HERRMAN Tomáš. Power Conscious RTL Test Scheduling. In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008, pp. 721-728. ISBN 978-0-7695-3277-6.
    Detail

    ANTOŠ David, ČEŠKA Milan, KOTÁSEK Zdeněk, KŘETÍNSKÝ Mojmír, MATYSKA Luděk and VOJNAR Tomáš, ed. Proceedings of 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2008. ISBN 978-80-7355-082-0.
    Detail

    STAREČEK Lukáš, SEKANINA Lukáš and KOTÁSEK Zdeněk. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, pp. 255-258. ISBN 978-1-4244-2276-0.
    Detail

    ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and HERRMAN Tomáš. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. Microprocessors and Microsystems, vol. 32, no. 5, pp. 296-302. ISSN 0141-9331.
    Detail

    STRAKA Martin, KOTÁSEK Zdeněk and WINTER Jan. The Design of Hardware Checkers for Verification and Diagnostic Purposes. In: CSE'2008 International Scientific Conference on Computer Science and Engineering. High Tatras - Stará Lesná: The University of Technology Košice, 2008, pp. 320-327. ISBN 978-80-8086-092-9.
    Detail

  • 2007

    KOTÁSEK Zdeněk and KUBEK Ján. Finite State Machine Localisation Based on IP Softcores Analysis. In: 6th Electronic Circuits and Systems Conference. Conference Proceedings. Bratislava: Slovak University of Technology in Bratislava, 2007, pp. 137-142. ISBN 978-80-227-2697-9.
    Detail

    STRAKA Martin, TOBOLA Jiří and KOTÁSEK Zdeněk. Checker Design for On-line Testing of Xilinx FPGA Communication. In: The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007, pp. 152-160. ISBN 0-7695-2885-6.
    Detail

    STRAKA Martin and KOTÁSEK Zdeněk. Checker for Communication Protocol between IP Cores Based on FPGA. In: 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Faculty of Informatics MU, 2007, pp. 193-200. ISBN 978-80-7355-077-6.
    Detail

    STAREČEK Lukáš, SEKANINA Lukáš, GAJDA Zbyšek, KOTÁSEK Zdeněk, PROKOP Roman and MUSIL Vladislav. On Properties and Utilization of Some Polymorphic Gates. In: 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology Slovak University of Technology in Bratislava, 2007, pp. 77-81. ISBN 978-80-227-2697-9.
    Detail

    TOBOLA Jiří, KOTÁSEK Zdeněk, KOŘENEK Jan, MARTÍNEK Tomáš and STRAKA Martin. Online Protocol Testing for FPGA Based Fault Tolerant Systems. In: 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007, pp. 676-679. ISBN 0-7695-2978-X.
    Detail

    ŠKARVADA Jaroslav, HERRMAN Tomáš and KOTÁSEK Zdeněk. RTL Testability Analysis Based on Circuit Partitioning and Its Link with Professional Tool. In: IEEE 8th Workshop on RTL and High Level Testing. Beijing: Institute of Computing Technology, Chinese Academy of Sciences, 2007, pp. 175-181.
    Detail

    ŠKARVADA Jaroslav, HERRMAN Tomáš and KOTÁSEK Zdeněk. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. In: 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007). Lübeck: IEEE Computer Society, 2007, pp. 611-618. ISBN 0-7695-2978-X.
    Detail

  • 2006

    SEKANINA Lukáš, STAREČEK Lukáš, GAJDA Zbyšek and KOTÁSEK Zdeněk. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006, pp. 186-193. ISBN 0-7695-2614-4.
    Detail

    PEČENKA Tomáš, KOTÁSEK Zdeněk and SEKANINA Lukáš. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 285-289. ISBN 1424401844.
    Detail

    ČERNÝ Stanislav, STRUŽKA Petr, KOŘENEK Jan, MARTÍNEK Tomáš and KOTÁSEK Zdeněk. FPGA Components in Simulink. In: Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006. Ostrava, 2006, pp. 158-163. ISBN 80-86840-26-3.
    Detail

    PEČENKA Tomáš and KOTÁSEK Zdeněk. I-path Scheduling Algorithm for RT Level Circuits. In: MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov, 2006, pp. 174-181. ISBN 80-214-3287-X.
    Detail

    SEKANINA Lukáš, STAREČEK Lukáš and KOTÁSEK Zdeněk. Novel Logic Circuits Controlled by Vdd. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 85-86. ISBN 1424401844.
    Detail

    KOTÁSEK Zdeněk and STRNADEL Josef. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, pp. 497-498. ISBN 0-7695-2546-6.
    Detail

    ŠKARVADA Jaroslav and KOTÁSEK Zdeněk. Systém pro podporu vzdělávání v oblasti plánování testu vestavěných systémů. In: Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006, pp. 319-321. ISBN 80-85645-56-4.
    Detail

    PEČENKA Tomáš, STRNADEL Josef, KOTÁSEK Zdeněk and SEKANINA Lukáš. Testability Estimation Based on Controllability and Observability Parameters. In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006, pp. 504-514. ISBN 0-7695-2609-8.
    Detail

  • 2005

    PEČENKA Tomáš, KOTÁSEK Zdeněk, SEKANINA Lukáš and STRNADEL Josef. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005, pp. 51-58. ISBN 0-7695-2399-4.
    Detail

    STRNADEL Josef and KOTÁSEK Zdeněk. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In: Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, pp. 420-427. ISBN 0-7695-2433-8.
    Detail

    DRÁBEK Vladimír and KOTÁSEK Zdeněk. Handbook of Testing Electronic Systems. Handbook of Testing Electronic Systems. Praha: Czech Technical University Publishing House, 2005, pp. 235-243. ISBN 80-01-03318-X.
    Detail

    KOTÁSEK Zdeněk, STRNADEL Josef and PEČENKA Tomáš. Methodology of Selecting Scan-Based Testability Improving Technique. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 186-189. ISBN 963-9364-48-7.
    Detail

    KOTÁSEK Zdeněk and STRNADEL Josef et al. Testing Tools for Training and Education. In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005, pp. 671-676. ISBN 83-919289-9-3.
    Detail

  • 2004

    KOTÁSEK Zdeněk, PEČENKA Tomáš, STRNADEL Josef, MIKA Daniel and SEKANINA Lukáš. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In: Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004, pp. 229-234. ISBN 80-8073-150-0.
    Detail

    KOTÁSEK Zdeněk, PEČENKA Tomáš, SEKANINA Lukáš and STRNADEL Josef. Evolutionary Design of Synthetic RTL Benchmark Circuits. In: Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004, pp. 107-108. ISBN 000000000.
    Detail

    KOTÁSEK Zdeněk, PEČENKA Tomáš and STRNADEL Josef. Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores. In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004, pp. 99-104. ISBN 80-969117-9-1.
    Detail

    KOTÁSEK Zdeněk and TUPEC Pavel. New approach to the FPGA testing based on the Boundary Scan. In: Proceedings of 38th International Conference MOSIS'04. Ostrava, 2004, pp. 120-123. ISBN 80-85988-98-4.
    Detail

    KOTÁSEK Zdeněk. Survey of Partial Scan Methodologies. In: Research and Training Action for System on Chip Design, 5th FP Project. Bratislava: Slovak Academy of Science, 2004, p. 77.
    Detail

    KOTÁSEK Zdeněk, MIKA Daniel and STRNADEL Josef. The Identification of Registers in RTL Structures. In: Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004. Technical Report TR-2004-6. Nicosia: Department of Computer Science of University of Cyprus, 2004, pp. 317-320. ISBN 3-540-41613.
    Detail

  • 2003

    MIKA Daniel and KOTÁSEK Zdeněk. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. In: Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2003, pp. 447-452. ISBN 0-08-044130-0.
    Detail

    KOTÁSEK Zdeněk, MIKA Daniel and STRNADEL Josef. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. In: Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003, pp. 233-238. ISBN 83-7143-557-6.
    Detail

    KOTÁSEK Zdeněk, RŮŽIČKA Richard and SEKANINA Lukáš, ed. Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia. Brno: Department of Computer Systems FIT BUT, 2003. ISBN 80-214-2471-0.
    Detail

    KOTÁSEK Zdeněk, MIKA Daniel and STRNADEL Josef. Test scheduling for embedded systems. In: Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003, pp. 463-467. ISBN 0-7695-2003-0.
    Detail

    KOTÁSEK Zdeněk, TUPEC Pavel and URBIŠ Hynek. Testing PCBs Based on Boundary Scan. In: Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003, pp. 119-122. ISBN 80-7099-509-2.
    Detail

    MIKA Daniel and KOTÁSEK Zdeněk. The Test Controller Model Based on The Timed Automaton. In: Proceedings of 37th International Conference MOSIS´03 Modelling and Simulation of Systems. Ostrava, 2003, pp. 107-114. ISBN 80-85988-86-0.
    Detail

    KOTÁSEK Zdeněk and URBIŠ Hynek. USB-to-IDE Adapter Design and Implementation. In: 6th International Workshopn on Electronics, Control, Measurment and Signals. Liberec: Liberec University of Technology, 2003, pp. 315-319. ISBN 80-7083-708-X.
    Detail

  • 2002

    STRNADEL Josef and KOTÁSEK Zdeněk. Normalized Testability Measures at RT Level: Utilization and Reasons for Creation. In: Proceedings of 36th International Conference MOSIS`02 Modeling and Simulation of Systems. Vol. I.. Ostrava, 2002, pp. 297-304. ISBN 80-85988-71-2.
    Detail

    STRNADEL Josef and KOTÁSEK Zdeněk. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. In: Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Brno University of Technology, 2002, pp. 44-51. ISBN 80-214-2094-4.
    Detail

    HLAVIČKA Jan, KOTÁSEK Zdeněk, MARINISSEN Erik Jan, NOVÁK Ondřej, RŮŽIČKA Richard and STRAUBE Bernd, ed. Proceedings of 5th International Workshop IEEE Design and Diagnostics of Electronic Circuits and Systems. Brno: Faculty of Information Technology BUT, 2002. ISBN 80-214-2094-4.
    Detail

    MIKA Daniel, KOTÁSEK Zdeněk and STRNADEL Josef. Test Controller Design Based on VHDL Source File Analysis. In: Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002, pp. 135-141. ISBN 80-7099-879-2.
    Detail

    STRNADEL Josef and KOTÁSEK Zdeněk. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. In: Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002, pp. 166-173. ISBN 0-7695-1790-0.
    Detail

    ZBOŘIL František V., KOTÁSEK Zdeněk, MIKA Daniel and STRNADEL Josef. The Identification of Feedback Loops in RTL Structures. In: Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002, pp. 142-147. ISBN 80-7099-879-2.
    Detail

  • 2001

    KOTÁSEK Zdeněk and STRNADEL Josef. Analytic Approach to RTL Testability Analysis. In: Proceedings of 7th Conference Student FEI 2001. Brno: Brno University of Technology, 2001, pp. 363-367. ISBN 80-214-1860-5.
    Detail

    KOTÁSEK Zdeněk, RŮŽIČKA Richard and STRNADEL Josef. Formal and Analytical Approaches to the Testability Analysis - the Comparison. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS Ltd., Hungary, 2001, pp. 123-128. ISBN 963-7175-16-4.
    Detail

    HLAVIČKA Jan, KOTÁSEK Zdeněk, RŮŽIČKA Richard and STRNADEL Josef. Interactive Tool for Behavioral Level Testability Analysis. In: Proceedings of the IEEE ETW 2001. Stockholm, 2001, pp. 117-119.
    Detail

    KOTÁSEK Zdeněk and STRNADEL Josef. RTL Testability Analysis Based on Genetic Algorithm Implementation. In: Proceedings of the Tenth ICNACSA. Plovdiv: unspecified agency, 2001, p. 1.
    Detail

    KOTÁSEK Zdeněk and STRNADEL Josef. RTL Testability Analysis Based on Genetic Algorithm Implementation. In: Proceedings of the IWCIT'01. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2001, pp. 83-88. ISBN 80-7078-907-7.
    Detail

    KOTÁSEK Zdeněk, RŮŽIČKA Richard, STRNADEL Josef and ZBOŘIL František. Two Level Testability System. In: Proceedings of the 35th Spring International Conference MOSIS'01. Ostrava, 2001, pp. 433-440. ISBN 80-85988-57-7.
    Detail

  • 2000

    KOTÁSEK Zdeněk and RŮŽIČKA Richard. Behavioral Analysis for Testability on VHDL Source File. In: Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshopsborník konference IEEE DDECS. Bratislava: Slovak Academy of Science, 2000, pp. 209-212. ISBN 80-968320-3.
    Detail

    HLAVIČKA Jan, KOTÁSEK Zdeněk and RŮŽIČKA Richard. Formal Approach to RTL Testability Analysis. In: sborník konference IEEE LATW 2000. Rio de Janeiro: unknown, 2000, pp. 98-103.
    Detail

    KOTÁSEK Zdeněk and RŮŽIČKA Richard. Partial Scan Methodologies - a Survey. In: sborník konference PDS2000. Ostrava: Elsevier Science, 2000, pp. 133-137. ISBN 0-08-043620-X.
    Detail

    KOTÁSEK Zdeněk and RŮŽIČKA Richard. Testability Analysis Based on Discrete Mathematics Concepts. In: Proc. of the 9-th International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 2000, p. 113.
    Detail

    KOTÁSEK Zdeněk and RŮŽIČKA Richard. The Implementation of RTL Testability Analysis Algorithms trough the Discrete Mathematics Concepts. In: Proc. of the Fourth International Scientific Conference on Electronic Computers and Informatics. Košice-Herľany: unknown, 2000, pp. 177-182. ISBN 80-88922-25-9.
    Detail

  • 1999

    KOTÁSEK Zdeněk and ZBOŘIL František. Neuronové sítě jako asociativní paměti. In: I&IT'99. Banská Bystrica: unknown, 1999, pp. 63-68. ISBN 80-8055-335-1.
    Detail

    KOTÁSEK Zdeněk. Partial Scan Methodologies - a Survey. In: sborník konference The Eighth International Colloquium on Numerical Analysis and Computer Science with Applications. Plovdiv: unknown, 1999, p. 110.
    Detail

    HLAVIČKA Jan, KOTÁSEK Zdeněk and ZBOŘIL František. Partial Scan Methodology for RTL Designs. In: Compendium of Papers ETW'99. Constance: unknown, 1999, p. 2. ISBN 0-7695-0390-X.
    Detail

    KOTÁSEK Zdeněk, RŮŽIČKA Richard and ZBOŘIL František. Partial Scan Methodology in VHDL Environment. In: CEI'99. Herľany: unknown, 1999, pp. 146-151. ISBN 80-88922-05-4.
    Detail

  • 1998

    KOTÁSEK Zdeněk and ZBOŘIL František. Boundary Scan of PCBs with Xilinx FPGAs. In: Sborník konference ECI98. Herlany: unknown, 1998, pp. 70-74. ISBN 80-88786-94-0.
    Detail

    KOTÁSEK Zdeněk and ZBOŘIL František. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In: Proceedings of the ECI'98. Herlany: Slovak Academy of Science, 1998, pp. 75-80. ISBN 80-88786-94-0.
    Detail

    KOTÁSEK Zdeněk, TOMÍŠEK Petr and ZBOŘIL František. Testing PCBs Based on Boundary Scan and EDIF Data Analysis. In: Proceedings of the DDECS'98. Szczyrk: unknown, 1998, pp. 95-101. ISBN 83-908409-6-0.
    Detail

  • 1997

    KOTÁSEK Zdeněk. RT Level Element Classification. In: Proceedings of the DDECS 97. Soláň: unknown, 1997, pp. 41-46. ISBN 80-85988-19-4.
    Detail

    BLATNÝ Jan, HLAVIČKA Jan and KOTÁSEK Zdeněk. RT Level Test Scheduling. Computer and Artificial Intelligence, vol. 14, no. 1, 1997, pp. 13-29. ISSN 0232-0274.
    Detail

    KOTÁSEK Zdeněk and ZBOŘIL František. RT Level Testability Analysis In PROLOG Enviroment. In: Proceedings of the DDECS'97. Ostrava, 1997, pp. 47-52. ISBN 80-85988-19-4.
    Detail

    KOTÁSEK Zdeněk and ZBOŘIL František. RT Level Testability Analysis to Reduce Test Application Time. In: Proceedings of the EUROMICRO 97. Budapest: unknown, 1997, pp. 104-111. ISBN 0-8186-8129-2.
    Detail

    HLAVIČKA Jan, KOTÁSEK Zdeněk and ZBOŘIL František. Test Overhead Reduction through RT Level Testability Analysis. In: Proceedings of the IEEE ETW 1997. Cagliary: unknown, 1997, pp. 43-47.
    Detail

  • 1995

    HLAVIČKA Jan, KOTÁSEK Petr and KOTÁSEK Zdeněk. RT Level Test Scheduling Procedure. In: Proceedings on Design Metodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995, pp. 264-271.
    Detail

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