Faculty of Information Technology, BUT


Zachariášová Marcela


Office L330


Research interests

  • Functional verification (SystemVerilog, OVM).
  • Hardware accelerated functional verification using FPGA technology.
  • Coverage driven verification using genetic programming and machine-learning algorithms. 
  • Design and testing of fault-tolerant systems.
  • Automated generation of verification environments.


  • HAVEN - Hardware-Accelerated Verification ENvironment


  • functional verification: presentation to PCS course [pdf, pptx], short version [pdf, pptx]
  • fault tolerance: presentation [pdf, pptx]


  • Acceleration of functional verification.
Nowadays, functional verification is a popular technique for verification of hardware systems. However, it is based on simulation and when complex systems are simulated, verification is quite time-demanding.

Our freely available and open-source acceleration framework HAVEN targets this issue and accelerates verification runs using the FPGA technology. Our experiments showed that this approach is very effective and we are able to speed-up the simulation more that 100 000 times.

Information and details about HAVEN can be found in technical papers:
  1. HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware
  2. Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures
  • The evaluation platform for testing fault-tolerance methodologies.

Other way, how to increase reliability of systems is to make use of the fault-tolerant system design. Currently, there exist different methodologies that can be used to harden systems against faults. Nevertheless, they are mostly tested on small designs. For this reason we implemented a testing platform which consists of several parts:

  1. An complex experimental design (the robot controller) which includes different aspects of hardware design (combinational and sequential logic, bus, memories). It allows testing different fault-tolerance methodologies targeted to specific design parts. The robot controller is implemented in VHDL and synthetised and placed into the FPGA. The aim of this unit is to find a path though the maze also in the presence of faults. Faults are artificially injected into the architecture of the robot controller.  
  2. The simulation environment Player/Stage allows to generate mazes for the robot and to monitor movements of the robot as well as the reactions of the system to faults. The simulation environment is running on the PC.
  3. The fault injector is situated also on the PC side and allows to inject faults directly to the FPGA, where the robot controller takes place, through the JTAG interface.
More information and details can be found in the following publications:
  1. Verification of Fault-tolerant Methodologies for FPGA Systems
  2. Robot Controller for Testing Fault-Tolerance

Short demonstration VIDEO.

Topics of BT/MT

  • functional verification of hardware systems
  • formal verification of hardware systems
  • hardware acceleration
  • genetic algorithms and genetic programming
  • machine-learning algorithms
  • fault-tolerant systems
  • ATPG (Automatic Test Pattern Generation)
  • fault testing


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