TASTE: Testability Analysis SuiTE
- create a structural model of digital design:
- Each design is represented by an object of clsDesign class. It is planned clsDesign object could consists of one ore more objects of clsCircuit class, each of them representing particular circuit within the design. In actual TASTE version, only one clsCircuit object is supported within a clsDesign object. The disadvantage shoud be removed in next TASTE version.
- Actually, clsCircuit object consists of one or more modules (objects of clsModule class) forming a structure and transparency behavior of the circuit.
- Next version of TASTE will be extended to modeling of hierarcical designs.
- Interfaces are assigned to clsDesign / clsCircuit / clsModule objects by means of clsPort and clsBit objects.
- Interconnections among clsDesign / clsCircuit / clsModule object interfaces are represented by means of clsWire objects.
- Example functions for loading necessary structural and transparency data are implemented in fileio.cc (header file fileio.h).
- run testability analysis (TA) over the modeled design:
- Functions for saving TA results in html, LaTEX and plain-text formats are offered in actual version of TASTE library and available only to clsCircuit objects. However, set of similar functions can be easily extended to more classes, formats etc.
- Optionally, it is possible to implement scan chains (popular design for testability (DFT) technique) into the original structure of the modeled circuit before TA is started. This can be, e.g., useful to study impacts of the technique to testability parameters of the circuit.
- Further DFT techniques as well as algorithms can be built over TASTE in a very easy way.
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