Project Details

SoC circuits reliability and availability improvement

Project Period: 1. 1. 2009 - 31. 12. 2011

Project Type: grant

Code: GA102/09/1668

Agency: Czech Science Foundation

Program: Standardní projekty

Czech title
Zvyšování spolehlivost a provozuschopnosti v obvodech SoC

fault tolerant systems, dependability


We propose a basic research project that is aimed at utilizing and deepening the current results of three research groups in the field of on-line and off-line testing and diagnostics with the intension to utilize them in the design of fault tolerant systems. The fault tolerant methodologies will be developed on three levels: level of error tolerance, level of single-event upset detection with additional reconfiguration and a level of system architecture graceful degradation in case of unrecoverable faults appearance. The goal of this project is to design a new, advanced design methodology for fault-tolerant circuits that will be based on the new technological possibilities.

Team members
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , research leader
Bartoš Pavel, Ing. (UPSY FIT VUT) , team leader
Kaštil Jan, Ing. (UPSY FIT VUT) , team leader
Mičulka Lukáš, Ing. (UPSY FIT VUT) , team leader
Slimařík František, Ing. (UPSY FIT VUT) , team leader
Straka Martin, Ing., Ph.D. (UPSY FIT VUT) , team leader
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT) , team leader






Back to top