Faculty of Information Technology, BUT

Publication Details

Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks

MATOUŠEK Jiří, SKAČAN Martin and KOŘENEK Jan. Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks. In: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013, pp. 108-111. ISBN 978-1-4673-6136-1.
Czech title
Návrh hardwarové architektury pro paměťově efektivní vyhledávání v IPv4/IPv6 směrovacích tabulkách ve 100 Gb/s sítích
Type
conference paper
Language
english
Authors
Matoušek Jiří, Ing., Ph.D. (DCSY FIT BUT)
Skačan Martin, Ing. (FIT BUT)
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)
Keywords
IP address, Longest Prefix Match, Memory
Abstract
With the growing speed of computer networks, core routers have to increase performance of longest prefix match (LPM) operation on IP addresses. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. To achieve 100 Gbps throughput, LPM operation has to be processed in dedicated hardware and a forwarding table has to fit into the on-chip memory. Current LPM algorithms need a large memory to store IPv6 forwarding tables or use compression with dynamic data structres, which can not be simply implemented in hardware. Therefore we provide analysis of available forwarding tables of core routers and propose a new representation of prefix sets. The proposed representation has very low memory demands and is suitable for high-speed pipelined processing, which is shown on new highly pipelined hardware architecture with 100 Gbps throughput.
Published
2013
Pages
108-111
Proceedings
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013, Karlovy Vary, CZ
ISBN
978-1-4673-6136-1
Publisher
IEEE Computer Society
Place
Brno, CZ
DOI
BibTeX
@INPROCEEDINGS{FITPUB10273,
   author = "Ji\v{r}\'{i} Matou\v{s}ek and Martin Ska\v{c}an and Jan Ko\v{r}enek",
   title = "Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks",
   pages = "108--111",
   booktitle = "2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS)",
   year = 2013,
   location = "Brno, CZ",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4673-6136-1",
   doi = "10.1109/DDECS.2013.6549798",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/10273"
}
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