Result Details

Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery

SZURMAN, K. Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery. Počítačové architektury & diagnostika 2013. Plzeň: University of West Bohemia in Pilsen, 2013. p. 21-26. ISBN: 978-1-4673-6136-1.
Type
conference paper
Language
English
Authors
Szurman Karel, Ing., Ph.D.
Abstract

The paper describes CAN Bus system implementation into the FPGA with usage of CANAerospace protocol. Control system is designed as Fault-tolerant and tested by the SEU injection. Text further discusses about state synchronization issue, which occurs after the system reconfiguration. The basic principles for resolving the synchronization after recovery are described.

Keywords

CAN, bus, CANAerospace, TMR, FPGA, SEU, recovery, state synchronization

Annotation
This paper describes the design of the FPGA-based CAN Bus control system and experiments which were performed with its reliability and SEU susceptibility. The control system architecture was implemented in the non-TMR and TMR versions. For experiments, previously developed external SEU generator was used which allows us to inject SEU failures randomly into the configuration memory of the running system. At the end of the paper main goals for my future research and Ph.D. thesis are presented the subject
of which will be the synchronization of fault-tolerant system after its failure and recovery.
Published
2013
Pages
21–26
Proceedings
Počítačové architektury & diagnostika 2013
ISBN
978-1-4673-6136-1
Publisher
University of West Bohemia in Pilsen
Place
Plzeň
BibTeX 
@inproceedings{BUT103571,
  author="Karel {Szurman}",
  title="Fault Tolerant CAN Bus Control System Implemented into FPGA and its synchronization after failure and recovery",
  booktitle="Počítačové architektury & diagnostika 2013",
  year="2013",
  pages="21--26",
  publisher="University of West Bohemia in Pilsen",
  address="Plzeň",
  isbn="978-1-4673-6136-1"
}
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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