Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA

 Regular expression matching is a time critical operation for any network security system. The NFA-Split is an efficient hardware architecture to match a large set of regular expressions at multigigabit speed with efficient FPGA logic utilization. Unfortunately, the matching speed is limited by processing only single byte in one clock cycle. Therefore, we propose new multi-stride NFA-Split architecture, which increases achievable throughput by processing multiple bytes per clock cycle.  Moreover, we investigate  efficiency of mapping DU to the FPGA logic and propose new  optimizations of mapping NFA-Split architecture to the FPGA. These optimizations are able to reduce up to 71.85% of FPGA LUTs and up to 94.18% of BlockRAMs.