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Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished

ČEŠKA Milan, MATYÁŠ Jiří, MRÁZEK Vojtěch, SEKANINA Lukáš, VAŠÍČEK Zdeněk and VOJNAR Tomáš. Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished. In: Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD). Irvine, CA: Institute of Electrical and Electronics Engineers, 2017, pp. 416-423. ISBN 978-1-5386-3093-8.
Czech title
Aproximace komplexních aritmetických obvodů s garantovanou chybou: 32-bitové násobičky
Type
conference paper
Language
english
Authors
Keywords
approximate computing, logical synthesis, genetic programming, formal methods
Abstract
We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the approximation error. The method integrates in a unique way formal techniques for approximate equivalence checking into a search-based circuit optimisation algorithm. The key idea of our approach is to employ a novel search strategy that drives the search towards promptly verifiable approximate circuits. The method was implemented within the ABC tool and extensively evaluated on functional approximation of multipliers (with up to 32-bit operands) and adders (with up to 128-bit operands). Within a few hours, we constructed a high-quality Pareto set of 32-bit multipliers providing trade-offs between the circuit error and size. This is for the first time when such complex
approximate circuits with formal error guarantees have been derived, which demonstrates an outstanding performance and scalability of our approach compared with existing methods that have either been applied to the approximation of multipliers limited to 8-bit operands or statistical testing has been used only. Our approach thus significantly improves capabilities of the existing methods and paves a way towards an automated design process of provably-correct circuit approximations.
Published
2017
Pages
416-423
Proceedings
Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)
Conference
IEEE/ACM International Conference On Computer-Aided Design, Irvine, CA, US
ISBN
978-1-5386-3093-8
Publisher
Institute of Electrical and Electronics Engineers
Place
Irvine, CA, US
DOI
BibTeX
@INPROCEEDINGS{FITPUB11420,
   author = "Milan \v{C}e\v{s}ka and Ji\v{r}\'{i} Maty\'{a}\v{s} and Vojt\v{e}ch Mr\'{a}zek and Luk\'{a}\v{s} Sekanina and Zden\v{e}k Va\v{s}\'{i}\v{c}ek and Tom\'{a}\v{s} Vojnar",
   title = "Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished",
   pages = "416--423",
   booktitle = "Proceedings of 36th IEEE/ACM International Conference On Computer Aided Design (ICCAD)",
   year = 2017,
   location = "Irvine, CA, US",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-5386-3093-8",
   doi = "10.1109/ICCAD.2017.8203807",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11420"
}
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