Faculty of Information Technology, BUT

Publication Details

Packet Classification with Limited Memory Resources

KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5.
Czech title
Klasifikace paketú s omezenými zdroji
Type
conference paper
Language
english
Authors
Kekely Michal, Ing. (DCSY FIT BUT)
Kořenek Jan, doc. Ing., Ph.D. (DCSY FIT BUT)
Keywords
DCFL, packet classification, FPGA, P4
Abstract
Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.
Published
2017
Pages
179-183
Proceedings
In proceedings 2017 Euromicro Conference on Digital System Design
Conference
20th Euromicro Conference on Digital Systems Design, Vídeň, AT
ISBN
978-1-5386-2145-5
Publisher
Institute of Electrical and Electronics Engineers
Place
Vieden, AT
DOI
BibTeX
@INPROCEEDINGS{FITPUB11550,
   author = "Michal Kekely and Jan Ko\v{r}enek",
   title = "Packet Classification with Limited Memory Resources",
   pages = "179--183",
   booktitle = "In proceedings 2017 Euromicro Conference on Digital System Design",
   year = 2017,
   location = "Vieden, AT",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-5386-2145-5",
   doi = "10.1109/DSD.2017.61",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11550"
}
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