Faculty of Information Technology, BUT

Publication Details

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018, pp. 129-134. ISBN 978-1-5386-5709-6.
Czech title
Částečná dynamická rekonfigurace v systémech odolných proti poruchám založených na FPGA: simulační vyhodnocení
Type
conference paper
Language
english
Authors
Pánek Richard, Ing. (DCSY FIT BUT)
Lojda Jakub, Ing. (DCSY FIT BUT)
Podivínský Jakub, Ing. (DCSY FIT BUT)
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Keywords
Fault Tolerant System, FPGA, Partial Reconfiguration, Simulation.
Abstract
Field Programmable Gate Arrays (FPGAs) are popular not only for their wide range of usage in embedded systems, however, they are susceptible to radiation effects. Charged particles cause the so-called Single Event Upsets (SEUs) in their configuration memory. SEUs can induce failure of the whole system. This problem is fundamental for space applications where sun radiation is more considerable than in the Earth. Two main approaches to SEU mitigation technique exist: fault masking and reparation. The most popular masking method is Triple Modular Redundancy (TMR). For the faults reparation, FPGA's capability of reconfiguration is used. It is possible to combine these approaches to obtain improved fault tolerant system. It is important to assess reliability rate of this system and, therefore, its estimation by a simulation is the main part of this paper. We propose evaluation environment which assesses the reliability of a TMR system with malfunction module reconfiguration depending on faults occurrence frequency and reconfiguration time necessary for fault reparation.
Published
2018
Pages
129-134
Proceedings
Proceedings of IEEE East-West Design & Test Symposium
Conference
16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM, Kazan, RU
ISBN
978-1-5386-5709-6
Publisher
IEEE Computer Society
Place
Kazaň, RU
DOI
BibTeX
@INPROCEEDINGS{FITPUB11758,
   author = "Richard P\'{a}nek and Jakub Lojda and Jakub Podiv\'{i}nsk\'{y} and Zden\v{e}k Kot\'{a}sek",
   title = "Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation",
   pages = "129--134",
   booktitle = "Proceedings of IEEE East-West Design \& Test Symposium",
   year = 2018,
   location = "Kaza\v{n}, RU",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-5386-5709-6",
   doi = "10.1109/EWDTS.2018.8524728",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/11758"
}
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