Result Details

Detecting hard synapses faults in artificial neural networks

KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Detecting hard synapses faults in artificial neural networks. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019. p. 1-6. ISBN: 978-1-7281-1756-0.

Type

conference paper

Language

English

Authors

Krčma Martin, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Lojda Jakub, Ing., Ph.D., DCSY (FIT)

Abstract

This paper presents the concepts of detecting hard faults in artificial neural network synapses using the modification of the neural network settings. The core of this work is based on weights values modification and inserting the chosen testing data when comparing the neural network output to the known valid results. The paper also discuss the problem of neural network output saturation and provide experiments on influence of the neural network settings to the problem in this regard.

Keywords

artificial neural networks, hard faults, faults detection, fault tolerance

Published

2019

Pages

1–6

Proceedings

20th IEEE Latin American Test Symposium (LATS 2019)

Conference

IEEE Latin American Test Symposium

ISBN

978-1-7281-1756-0

Publisher

IEEE Computer Society

Place

Santiago de Chile

DOI

10.1109/LATW.2019.8704637

UT WoS

000469850000035

EID Scopus

2-s2.0-85065958948

BibTeX

@inproceedings{BUT159964,
  author="Martin {Krčma} and Zdeněk {Kotásek} and Jakub {Lojda}",
  title="Detecting hard synapses faults in artificial neural networks",
  booktitle="20th IEEE Latin American Test Symposium (LATS 2019)",
  year="2019",
  pages="1--6",
  publisher="IEEE Computer Society",
  address="Santiago de Chile",
  doi="10.1109/LATW.2019.8704637",
  isbn="978-1-7281-1756-0",
  url="https://www.fit.vut.cz/research/publication/11876/"
}

Files

pdf 08704637.pdf 417 kB

Projects

IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, start: 2016-01-01, end: 2020-12-31, completed
Pokročilé paralelní a vestavěné počítačové systémy, BUT, Vnitřní projekty VUT, FIT-S-17-3994, start: 2017-03-01, end: 2020-02-29, completed

Research groups

Dependable Digital Systems Research Group (RG DEPSYS)

Departments

Department of Computer Systems (DCSY)