Publication Details

FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators

MARCHISIO Alberto, MRÁZEK Vojtěch, HANIF Muhammad A. and SHAFIQUE Muhammad. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, 2021, pp. 716-729. ISSN 1063-8210. Available from: https://ieeexplore.ieee.org/document/9363276/
Czech title
FEECA: Prohledávání stavového prostoru pro návrh rychlých a energeticky efektivních akcelerátorů kapsulových neuronových sítí
Type
journal article
Language
english
Authors
Marchisio Alberto (TU-Wien)
Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)
Hanif Muhammad A. (TU-Wien)
Shafique Muhammad (TU-Wien)
URL
Keywords

capsule neural network, hardware accelerators, design space exploration

Abstract

In the past few years, Capsule Networks (CapsNets) have taken the spotlight compared to traditional convolutional neural networks (CNNs) for image classification. Unlike CNNs, CapsNets have the ability to learn the spatial relationship between features of the images. However, their complexity grows because of their heterogeneous capsule structure and the dynamic routing, which is an iterative algorithm to dynamically learn the coupling coefficients of two consecutive capsule layers. This necessitates specialized hardware accelerators for CapsNets. Moreover, a high-performance and energy-efficient design of CapsNet accelerators requires exploration of different design decisions (such as the size and configuration of the processing array and the structure of the processing elements). Toward this, we make the following key contributions: 1) FEECA, a novel methodology to explore the design space of the (micro)architectural parameters of a CapsNet hardware accelerator and 2) CapsAcc, the first specialized RTL-level hardware architecture to perform CapsNets inference with high performance and high energy efficiency. Our CapsAcc achieves significant performance improvement, compared to an optimized GPU implementation, due to its efficient implementation of key activation functions, such as squash and softmax, and an efficient data reuse for the dynamic routing. The FEECA methodology employs the Non-dominated Sorting Genetic Algorithm (NSGA-II) to explore the Pareto-optimal points with respect to area, performance, and energy consumption. This requires analytical modeling of the number of clock cycles required to perform each operation of the CapsNet inference and the memory accesses to enable a fast yet accurate design space exploration. We synthesized the complete accelerator architecture in a 45-nm CMOS technology using Synopsys design tools and evaluated it for the MNIST benchmark (as done by the original CapsNet paper from Google Brain's team) and for a more complex data set, the German Traffic Sign Recognition Benchmark (GTSRB).

Published
2021
Pages
716-729
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, ISSN 1063-8210
Publisher
IEEE Computer Society
DOI
UT WoS
000637190300011
EID Scopus
BibTeX
@ARTICLE{FITPUB12426,
   author = "Alberto Marchisio and Vojt\v{e}ch Mr\'{a}zek and A. Muhammad Hanif and Muhammad Shafique",
   title = "FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators",
   pages = "716--729",
   journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
   volume = 29,
   number = 4,
   year = 2021,
   ISSN = "1063-8210",
   doi = "10.1109/TVLSI.2021.3059518",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/12426"
}
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