Publication Details

Optimization of BDD-based Approximation Error Metrics Calculations

MRÁZEK Vojtěch. Optimization of BDD-based Approximation Error Metrics Calculations. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22). Paphos: Institute of Electrical and Electronics Engineers, 2022, pp. 86-91. ISBN 978-1-6654-6605-9.

Czech title

Öptimalizace výpočtu aproximační chyby založeného na BDD

Type

conference paper

Language

english

Authors

Mrázek Vojtěch, Ing., Ph.D. (DCSY FIT BUT)

Keywords

approximate computing, error evaluation, relaxed equivalence checking

Published

2022

Pages

86-91

Proceedings

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)

Conference

2022 IEEE Computer Society Annual Symposium on VLSI, Kypr, CY

ISBN

978-1-6654-6605-9

Publisher

Institute of Electrical and Electronics Engineers

Place

Paphos, CY

DOI

10.1109/ISVLSI54635.2022.00028

UT WoS

000886230500015

EID Scopus

2-s2.0-85140915424

BibTeX

@INPROCEEDINGS{FITPUB12698,
   author = "Vojt\v{e}ch Mr\'{a}zek",
   title = "Optimization of BDD-based Approximation Error Metrics Calculations",
   pages = "86--91",
   booktitle = "IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)",
   year = 2022,
   location = "Paphos, CY",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-6654-6605-9",
   doi = "10.1109/ISVLSI54635.2022.00028",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/12698"
}