Result Details
Testable Design Verification Using Petri Nets
        RŮŽIČKA, R. Testable Design Verification Using Petri Nets. Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003. p. 304-311.  ISBN: 0-7695-2003-0.
    
                Type
            
        
                conference paper
            
        
                Language
            
        
                English
            
        
            Authors
            
        
                    Abstract
            
        In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.
                Keywords
            
        Testability Analysis, Testability Verification, Petri Nets, I path, RTL Digital Circuits
                Published
            
            
                    2003
                    
                
            
                    Pages
                
            
                        304–311
                
            
                        Proceedings
                
            
                    Proceedings of Euromicro Symposium on Digital System Design 2003
                
            
                    Conference
                
            
                    EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools
                
            
                    ISBN
                
            
                    0-7695-2003-0
                
            
                    Publisher
                
            
                    IEEE Computer Society Press
                
            
                    Place
                
            
                    Los Alamitos, CA
                
            
                    BibTeX
                
            @inproceedings{BUT14194,
  author="Richard {Růžička}",
  title="Testable Design Verification Using Petri Nets",
  booktitle="Proceedings of Euromicro Symposium on Digital System Design 2003",
  year="2003",
  pages="304--311",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos, CA",
  isbn="0-7695-2003-0"
}
                Projects
            
        
        
            
        
    
    
        Formal approach to digital circuits test scheduling, GACR, Postdoktorandské granty, GP102/03/P176, start: 2003-01-01, end: 2005-12-31, completed
                
Formal Approaches in Digital Design Diagnostics - Testable Design Verification, GACR, Standardní projekty, GA102/01/1531, start: 2001-01-01, end: 2003-12-31, completed
        Formal Approaches in Digital Design Diagnostics - Testable Design Verification, GACR, Standardní projekty, GA102/01/1531, start: 2001-01-01, end: 2003-12-31, completed
                Research groups
            
        
                Departments