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An Evolvable Combinational Unit for FPGAs

SEKANINA Lukáš and FRIEDL Štěpán. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, vol. 23, no. 5, pp. 461-486. ISSN 1335-9150.
Czech title
Vyvíjející se kombinační jednotka pro FPGA
Type
journal article
Language
english
Authors
URL
Keywords
combinational circuit, evolutionary design, evolvable hardware, field programmable gate array
Abstract
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.
Published
2004
Pages
461-486
Journal
Computing and Informatics, vol. 23, no. 5, ISSN 1335-9150
Publisher
Slovak Academic Press
BibTeX
@ARTICLE{FITPUB7741,
   author = "Luk\'{a}\v{s} Sekanina and \v{S}t\v{e}p\'{a}n Friedl",
   title = "An Evolvable Combinational Unit for FPGAs",
   pages = "461--486",
   journal = "Computing and Informatics",
   volume = 23,
   number = 5,
   year = 2004,
   ISSN = "1335-9150",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7741"
}
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