High-level Modeling, Analysis and Verification of Programmable Hardware Design
formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis
This work presents an abstract model of the design and verification of several safety properties. The main task was to check if there is a risk of buffer overflow and how to set the length of buffers to prevent this. This work shows how to model such a complex system by hand and particular results of analysis and verification is also presented.