Faculty of Information Technology, BUT

Publication Details

High-level Modeling, Analysis and Verification of Programmable Hardware Design

SMRČKA Aleš. High-level Modeling, Analysis and Verification of Programmable Hardware Design. Proceedings of the Junior Scientist Conference 2006. Vienna: TU Vienna, 2006. ISBN 3-902463-05-8.
Czech title
Vysokoúrovňové modelování, analýza a verifikace programovatelného hardwarového návrhu
Type
abstract
Language
english
Authors
Keywords
formal verification, high-level verification, hardware design analysis, throughput checking, timed analysis
Abstract
This work presents an abstract model of the design and verification of several safety properties. The main task was to check if there is a risk of buffer overflow and how to set the length of buffers to prevent this. This work shows how to model such a complex system by hand and particular results of analysis and verification is also presented.
Published
2006
Pages
93-94
Book
Proceedings of the Junior Scientist Conference 2006
Conference
Junior Scientist Conference 2006, Vídeň, AT
ISBN
3-902463-05-8
Publisher
TU Vienna
Place
Vienna, AT
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