Result Details
Test Controller Synthesis Constrained by Circuit Testability Analysis
RŮŽIČKA, R.; STRNADEL, J. Test Controller Synthesis Constrained by Circuit Testability Analysis. Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007. p. 626-633. ISBN: 0-7695-2978-X.
Type
conference paper
Language
English
Authors
Abstract
In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.
Keywords
testability analysis, test controller, RTL digital circuit diagnostics
Published
2007
Pages
626–633
Proceedings
Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Conference
10th EUROMICRO Conference on Digital System Design
ISBN
0-7695-2978-X
Publisher
IEEE Computer Society Press
Place
Los Alamitos
BibTeX
@inproceedings{BUT28840,
author="Richard {Růžička} and Josef {Strnadel}",
title="Test Controller Synthesis Constrained by Circuit Testability Analysis",
booktitle="Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools",
year="2007",
pages="626--633",
publisher="IEEE Computer Society Press",
address="Los Alamitos",
isbn="0-7695-2978-X"
}
Projects
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments