Publication Details
The Design of Hardware Checkers for Verification and Diagnostic Purposes
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Winter Jan, Ing. (DCSY FIT BUT)
on-line checker, on-line testing, verification, PSL, FPGA, FoCs, ModelSim
In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components is described. First, our experiments with PSL language and FoCs tool are demonstrated. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principles of our approach based on developing a formal language to describe the functions to be checked and a compiler which transforms the description into VHDL code are explained.
@INPROCEEDINGS{FITPUB8646,
author = "Martin Straka and Zden\v{e}k Kot\'{a}sek and Jan Winter",
title = "The Design of Hardware Checkers for Verification and Diagnostic Purposes",
pages = "320--327",
booktitle = "CSE'2008 International Scientific Conference on Computer Science and Engineering",
year = 2008,
location = "High Tatras - Star\'{a} Lesn\'{a}, SK",
publisher = "The University of Technology Ko\v{s}ice",
ISBN = "978-80-8086-092-9",
language = "english",
url = "https://www.fit.vut.cz/research/publication/8646"
}