Faculty of Information Technology, BUT

Publication Details

Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration

STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. In: 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010, pp. 365-372. ISBN 978-0-7695-4171-6.
Czech title
Struktura odolného systému pro SRAM FPGA s využitím částečné dynamické rekonfigurace
Type
conference paper
Language
english
Authors
Keywords
fault tolerant systems, reconfiguration, controller, FPGA, architecture
Abstract

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Annotation

In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.

Published
2010
Pages
365-372
Proceedings
13th EUROMICRO Conference on Digital System Design, DSD'2010
Conference
13th EUROMICRO Conference on Digital System Design, DSD'2010, Lille, FR
ISBN
978-0-7695-4171-6
Publisher
IEEE Computer Society
Place
Lille, FR
BibTeX
@INPROCEEDINGS{FITPUB9208,
   author = "Martin Straka and Jan Ka\v{s}til and Zden\v{e}k Kot\'{a}sek",
   title = "Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration",
   pages = "365--372",
   booktitle = "13th EUROMICRO Conference on Digital System Design, DSD'2010",
   year = 2010,
   location = "Lille, FR",
   publisher = "IEEE Computer Society",
   ISBN = "978-0-7695-4171-6",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9208"
}
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