Faculty of Information Technology, BUT

Publication Details

Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints

KŘOUSTEK Jakub, ŽIDEK Stanislav, KOLÁŘ Dušan and MEDUNA Alexander. Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints. In: Proceedings of the 12th Biennial Baltic Electronics Conference. Tallinn: Institute of Electrical and Electronics Engineers, 2010, pp. 165-168. ISBN 978-1-4244-7357-1. Available from: https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5630284
Czech title
Využití gramatik s rozptýleným kontextem k modelování omezení instrukcí VLIW procesoru
Type
conference paper
Language
english
Authors
URL
Keywords
scattered context grammar, SCG, VLIW, assembler, conflicts, latency
Abstract
More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler.

This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.
Published
2010
Pages
165-168
Proceedings
Proceedings of the 12th Biennial Baltic Electronics Conference
Conference
12th Biennial Baltic Electronics Conference, Tallinn, EE
ISBN
978-1-4244-7357-1
Publisher
Institute of Electrical and Electronics Engineers
Place
Tallinn, EE
DOI
BibTeX
@INPROCEEDINGS{FITPUB9233,
   author = "Jakub K\v{r}oustek and Stanislav \v{Z}idek and Du\v{s}an Kol\'{a}\v{r} and Alexander Meduna",
   title = "Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints",
   pages = "165--168",
   booktitle = "Proceedings of the 12th Biennial Baltic Electronics Conference",
   year = 2010,
   location = "Tallinn, EE",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "978-1-4244-7357-1",
   doi = "10.1109/BEC.2010.5630284",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9233"
}
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