Result Details
Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA
Kaštil Jan, Ing., Ph.D., DIFS (FIT), DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
FPGA, partial reconfiguration, controller, fault tolerant system, architecture
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
@inproceedings{BUT34857,
author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA",
booktitle="NORCHIP 2010",
year="2010",
pages="1--4",
publisher="IEEE Computer Society",
address="Tampere",
isbn="978-1-4244-8971-8"
}Secured, reliable and adaptive computer systems, BUT, Vnitřní projekty VUT, FIT-S-10-1, start: 2010-03-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed