Faculty of Information Technology, BUT

Publication Details

Fast Just-In-Time Translated Simulation for ASIP Design

PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš and KOLÁŘ Dušan. Fast Just-In-Time Translated Simulator for ASIP Design. In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011, pp. 279-282. ISBN 978-1-4244-9753-9.
Czech title
Rychlý Just-In-Time překládaný simulátor pro vývoj ASIPů
Type
conference paper
Language
english
Authors
Keywords
Architecture description languages, simulation, testing, application-specific instruction set processors
Abstract
The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.
Published
2011
Pages
279-282
Proceedings
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011, Cottbus, DE
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus, DE
DOI
BibTeX
@INPROCEEDINGS{FITPUB9567,
   author = "Zden\v{e}k P\v{r}ikryl and Jakub K\v{r}oustek and Tom\'{a}\v{s} Hru\v{s}ka and Du\v{s}an Kol\'{a}\v{r}",
   title = "Fast Just-In-Time Translated Simulation for ASIP Design",
   pages = "279--282",
   booktitle = "14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
   year = 2011,
   location = "Cottbus, DE",
   publisher = "IEEE Computer Society",
   ISBN = "978-1-4244-9753-9",
   doi = "10.1109/DDECS.2011.5783094",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9567"
}
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