Faculty of Information Technology, BUT

Publication Details

Hardware Accelerated Functional Verification

ZACHARIÁŠOVÁ Marcela. Hardware Accelerated Functional Verification. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Faculty of Information Technology BUT, 2011, pp. 321-323. ISBN 978-80-214-4272-6.
Czech title
Hardwarově akcelerovaná funkční verifikace
Type
conference paper
Language
english
Authors
URL
Keywords
functional verification, testbench, SystemVerilog, hardware acceleration, FPGA
Abstract
Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. We introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.
Published
2011
Pages
321-323
Proceedings
Proceedings of the 17th Conference STUDENT EEICT 2011
Conference
Student EEICT 2011, Brno, CZ
ISBN
978-80-214-4272-6
Publisher
Faculty of Information Technology BUT
Place
Brno, CZ
BibTeX
@INPROCEEDINGS{FITPUB9705,
   author = "Marcela Zachari\'{a}\v{s}ov\'{a}",
   title = "Hardware Accelerated Functional Verification",
   pages = "321--323",
   booktitle = "Proceedings of the 17th Conference STUDENT EEICT 2011",
   year = 2011,
   location = "Brno, CZ",
   publisher = "Faculty of Information Technology BUT",
   ISBN = "978-80-214-4272-6",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/9705"
}
Back to top