Faculty of Information Technology, BUT

Publication Details

FPGA-Based Packet Generator

MATOUŠEK Jiří. FPGA-Based Packet Generator. In: Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Brno University of Technology, 2011, pp. 312-314. ISBN 978-80-214-4272-6. Available from: http://www.feec.vutbr.cz/conf/EEICT/archiv/sborniky/EEICT_2011_sbornik/02-Magisterske%20projekty/10-Pocitacove%20systemy/07-xmatou06.pdf
English title
FPGA-Based Packet Generator
Type
conference paper
Language
czech
Authors
URL
Keywords
packet generator, NetCOPE, COMBOv2, 10 Gigabit Ethernet, timestamp
Abstract
Current backbone networks operate at speed of tens of Gb/s. Devices for these networks have to be tested properly at full wire speed. This implies the need for a testing device able to replay and/or generate network traffic at this speed. This paper describes a novel architecture of a high-speed network packet generator based on the NetCOPE platform and the COMBOv2 card. Proposed device is to be implemented in the FPGA chip and it will allow replaying and generating network traffic at full wire speed of two 10 Gb/s network interfaces. As an optional feature, limiting of transmitted traffic based on precise 64-bit timestamps will be included. This will allow users to perform time-critical experiments requiring precisely defined inter-packet delays.
Published
2011
Pages
312-314
Proceedings
Proceedings of the 17th Conference STUDENT EEICT 2011
Conference
Student EEICT 2011, Brno, CZ
ISBN
978-80-214-4272-6
Publisher
Brno University of Technology
Place
Brno, CZ
BibTeX
@INPROCEEDINGS{FITPUB9788,
   author = "Ji\v{r}\'{i} Matou\v{s}ek",
   title = "FPGA-Based Packet Generator",
   pages = "312--314",
   booktitle = "Proceedings of the 17th Conference STUDENT EEICT 2011",
   year = 2011,
   location = "Brno, CZ",
   publisher = "Brno University of Technology",
   ISBN = "978-80-214-4272-6",
   language = "czech",
   url = "https://www.fit.vut.cz/research/publication/9788"
}
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