Publication Details
Delay-aware evolutionary optimization of digital circuits
Logic optimization, Cartesian Genetic Program- ming, Evolutionary Resynthesis
In the recent years, machine learning techniques have successfully been applied
in various areas of digital circuit design including logic synthesis.
Evolutionary resynthesis, among others, represents one of the machine learning
approaches. This technique is based on local iterative optimization of parts of
the original circuit. Even though the local optimization could be inefficient
compared to the optimization conducted on the whole circuits, it has been shown
that the resynthesis performs extremely well. It produces more compact solutions
compared to the state-of-the art synthesis methods. In addition, it scales
significantly better compared to the evolutionary optimization performed at the
level of the original circuit. The previous methods have been focused solely on
the optimization of the number of gates. In this paper, we analyse how the local
optimization affects the delay of the resulting circuits and based on that, we
propose a modified approach that considers the delay in the course of the
optimization process. The proposed modification enables to maintain the delay of
the optimized circuit at a reasonable level without a significant overhead. The
evaluation conducted on a set of non-trivial highly optimized benchmark circuits
representing various real-world circuits demonstrated that the proposed method is
able to remove a significant number of gates while preserving the delay within
the requested bounds.
@inproceedings{BUT178169,
author="Jitka {Kocnová} and Zdeněk {Vašíček}",
title="Delay-aware evolutionary optimization of digital circuits",
booktitle="Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
year="2022",
pages="188--193",
publisher="IEEE Computer Society",
address="Nicosia, Cyprus",
doi="10.1109/ISVLSI54635.2022.00045",
isbn="978-1-6654-6605-9"
}