Result Details
Methodology for Design of Highly Dependable Systems in FPGA
Kaštil Jan, Ing., Ph.D., DIFS (FIT), DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.
system design, fault tolerance, architecture, reconfiguration, FPGA, soft error, methodology
In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design highly dependable system in FPGA is described. First, our experiences with partial dynamic reconfiguration in FPGA and application of partial reconfiguration as advanced solution for constructing of different types of fault tolerant architectures are described. Secondly, the main principles of methodology and first experiments with real fault tolerant designs based on partial dynamic reconfiguration implemented into Virtex5 and latest Virtex6 FPGAs are demonstrated.
@inproceedings{BUT35527,
author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}",
title="Methodology for Design of Highly Dependable Systems in FPGA",
booktitle="International Scientific Conference on Computer Science and Engineering",
year="2010",
pages="186--193",
publisher="The University of Technology Košice",
address="Košice",
isbn="978-80-8086-164-3"
}
Secured, reliable and adaptive computer systems, BUT, Vnitřní projekty VUT, FIT-S-10-1, start: 2010-03-01, end: 2010-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
SoC circuits reliability and availability improvement, GACR, Standardní projekty, GA102/09/1668, start: 2009-01-01, end: 2011-12-31, completed