Result Details

Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area

MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013. p. 227-234. ISBN: 978-0-7695-5074-9.
Type
conference paper
Language
English
Authors
Mičulka Lukáš, Ing., Ph.D.
Straka Martin, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.

Keywords

methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space

Published
2013
Pages
227–234
Proceedings
16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Conference
16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
ISBN
978-0-7695-5074-9
Publisher
IEEE Computer Society
Place
Santander
BibTeX 
@inproceedings{BUT103518,
  author="Lukáš {Mičulka} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area",
  booktitle="16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools",
  year="2013",
  pages="227--234",
  publisher="IEEE Computer Society",
  address="Santander",
  isbn="978-0-7695-5074-9"
}
Projects
Advanced secured, reliable and adaptive IT, BUT, Vnitřní projekty VUT, FIT-S-11-1, start: 2011-01-01, end: 2013-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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