Result Details

A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP

GROCHOL, D.; SEKANINA, L.; ŽÁDNÍK, M.; KOŘENEK, J. A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. In Applications of Evolutionary Computation, 18th European Conference. Lecture Notes in Computer Science. Berlin: Springer International Publishing, 2015. p. 67-78. ISBN: 978-3-319-16548-6.
Type
conference paper
Language
English
Authors
Grochol David, Ing., Ph.D., DCSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Žádník Martin, Ing., Ph.D., DCSY (FIT)
Kořenek Jan, doc. Ing., Ph.D., DCSY (FIT)
Abstract

This paper deals with design of an application protocol classifier intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array. The classification is performed using the first packet carrying the application payload. In order to further reduce the latency, the circuit is optimized by Cartesian genetic programming. Using a real network data, we demonstrated viability of our approach in task of a very fast classification of three application protocols (HTTP, SMTP, SSH).

Keywords

computer network, cartesian genetic programming, classifier, FPGA

Published
2015
Pages
67–78
Proceedings
Applications of Evolutionary Computation, 18th European Conference
Series
Lecture Notes in Computer Science
Volume
9028
Conference
Applications of Evolutionary Computation, 18th European Conference
ISBN
978-3-319-16548-6
Publisher
Springer International Publishing
Place
Berlin
DOI
10.1007/978-3-319-16549-3_6
EID Scopus
2-s2.0-84925874328
BibTeX 
@inproceedings{BUT119801,
  author="David {Grochol} and Lukáš {Sekanina} and Martin {Žádník} and Jan {Kořenek}",
  title="A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP",
  booktitle="Applications of Evolutionary Computation, 18th European Conference",
  year="2015",
  series="Lecture Notes in Computer Science",
  volume="9028",
  pages="67--78",
  publisher="Springer International Publishing",
  address="Berlin",
  doi="10.1007/978-3-319-16549-3\{_}6",
  isbn="978-3-319-16548-6",
  url="https://www.fit.vut.cz/research/publication/10772/"
}
Files
Projects
Advanced Methods for Evolutionary Design of Complex Digital Circuits, GACR, Standardní projekty, GA14-04197S, start: 2014-01-01, end: 2016-12-31, completed
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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