Result Details

FPGA Prototyping and Accelerated Verification of ASIPs

PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3.
Type
conference paper
Language
English
Authors
Podivínský Jakub, Ing., Ph.D., DCSY (FIT)
Zachariášová Marcela, Ing., Ph.D., DCSY (FIT)
Čekan Ondřej, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

Keywords

UVM, Acceleration, FPGA Prototyping, ASIP

Published
2015
Pages
145–148
Proceedings
IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Conference
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2015
ISBN
978-1-4799-6780-3
Publisher
IEEE Computer Society
Place
Belgrade
DOI
10.1109/DDECS.2015.33
EID Scopus
2-s2.0-84954127051
BibTeX 
@inproceedings{BUT119854,
  author="Jakub {Podivínský} and Marcela {Zachariášová} and Ondřej {Čekan} and Zdeněk {Kotásek}",
  title="FPGA Prototyping and Accelerated Verification of ASIPs",
  booktitle="IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2015",
  pages="145--148",
  publisher="IEEE Computer Society",
  address="Belgrade",
  doi="10.1109/DDECS.2015.33",
  isbn="978-1-4799-6780-3",
  url="https://www.fit.vut.cz/research/publication/10881/"
}
Files
Projects
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Centrum excelence IT4Innovations, MŠMT, Operační program Výzkum a vývoj pro inovace, ED1.1.00/02.0070, start: 2011-01-01, end: 2015-12-31, completed
Manufacturable and Dependable Multicore Architectures at Nanoscale, MŠMT, COST, COST IC1103, start: 2011-06-15, end: 2015-12-31, completed
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, start: 2012-03-01, end: 2015-11-30, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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