Result Details

Advanced Parallel Copula Based EDA

HYRŠ, M.; SCHWARZ, J. Advanced Parallel Copula Based EDA. In 2016 IEEE Symposium Series on Computational Intelligence. Athens: Institute of Electrical and Electronics Engineers, 2016. p. 1-8. ISBN: 978-1-5090-4239-5.
Type
conference paper
Language
English
Authors
Hyrš Martin, Ing., Ph.D., DCSY (FIT)
Schwarz Josef, doc. Ing., CSc., DCSY (FIT)
Abstract


Estimation of distribution algorithms (EDAs) are

stochastic optimization techniques that are based on building and
sampling a probability model. Copula theory provides methods
that simplify the estimation of the probability model. To improve
the efficiency of current copula based EDAs (CEDAs) new modifications
of parallel CEDA were proposed. We investigated eight
variants of island-based algorithms utilizing the capability of
promising copula families, inter-island migration and additional
adaptation of marginal parameters using CT-AVS technique.
The proposed algorithms were tested on two sets of well-known
standard optimization benchmarks in the continuous domain.
The results of the experiments validate the efficiency of our
algorithms.

Keywords

Estimation of distribution algorithm (EDA)
Copula theory
Parallel island-based algorithm
Migration of model
Benchmarks CEC 2013

Published
2016
Pages
1–8
Proceedings
2016 IEEE Symposium Series on Computational Intelligence
Conference
IEEE Symposium Series on Computational Intelligence 2016
ISBN
978-1-5090-4239-5
Publisher
Institute of Electrical and Electronics Engineers
Place
Athens
DOI
UT WoS
000400488302108
EID Scopus
BibTeX
@inproceedings{BUT133499,
  author="Martin {Hyrš} and Josef {Schwarz}",
  title="Advanced Parallel Copula Based EDA",
  booktitle="2016 IEEE Symposium Series on Computational Intelligence",
  year="2016",
  pages="1--8",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Athens",
  doi="10.1109/SSCI.2016.7850202",
  isbn="978-1-5090-4239-5",
  url="https://www.fit.vut.cz/research/publication/11225/"
}
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Projects
Architektury paralelních a vestavěných počítačových systémů, BUT, Vnitřní projekty VUT, FIT-S-14-2297, start: 2014-01-01, end: 2016-12-31, completed
Departments
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