Result Details
Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming
The aim of the paper is to introduce a new parallel approach to evolutionary optimization of digital circuits described on transistor level. The evolutionary optimization is guided by the fitness function employing a simulator of candidate circuits. A new discrete simulator was introduced to achieve a good trade-off between precision and cost of circuit evaluations. The simulator is based on event-driven simulation. Precise numeric SPICE simulator is regularly called to validate simulation results. To increase the speed of evolution, three parallel approaches were proposed: (i) thread level parallelism, (ii) multiple computing nodes which collectively communicate and distribute the best solution, and (iii) client-server architecture eliminating a limited count of SPICE simulator instances.
Evolutionary optimization, transistor-level, parallel systems, digitalcircuits
@inproceedings{BUT144422,
author="Vojtěch {Mrázek} and Zdeněk {Vašíček}",
title="Parallel Optimization of Transistor Level Circuits using Cartesian Genetic Programming",
booktitle="GECCO Companion '17 Proceedings of the Companion Publication of the 2017 on Genetic and Evolutionary Computation Conference",
year="2017",
pages="1849--1856",
publisher="Association for Computing Machinery",
address="Berlin",
doi="10.1145/3067695.3084212",
isbn="978-1-4503-4939-0",
url="https://www.fit.vut.cz/research/publication/11377/"
}