Result Details

Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria

MRÁZEK, V.; VAŠÍČEK, Z. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018. p. 294-295. ISBN: 978-1-4503-5764-7.
Type
conference paper
Language
English
Authors
Abstract

As a promising approach to the design of energy efficient circuits, approximate circuits and approximate circuit design methodologies have attracted a significant attention of researchers as well as industry. Compared to the traditional design methods, it has been demonstrated that evolutionary approaches are able to discover approximate circuits exhibiting a good trade-off between the energy consumption and circuit quality. In this work, evolutionary design of large approximate adders is addressed. In order to improve scalability, the quality of the candidate solutions is analysed using a formal approach based on Binary Decision Diagrams. Compared to the common approach based on a parallel circuit simulator, the proposed method is able to evaluate 2-3 orders of magnitude more generations.

Keywords

Approximate computing, genetic algorithm, equivalence checking

Published
2018
Pages
294–295
Proceedings
Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18)
Conference
Genetic and Evolutionary Computations Conference 2018
ISBN
978-1-4503-5764-7
Publisher
Association for Computing Machinery
Place
Kyoto
DOI
EID Scopus
BibTeX
@inproceedings{BUT155006,
  author="Vojtěch {Mrázek} and Zdeněk {Vašíček}",
  title="Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria",
  booktitle="Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18)",
  year="2018",
  pages="294--295",
  publisher="Association for Computing Machinery",
  address="Kyoto",
  doi="10.1145/3205651.3205678",
  isbn="978-1-4503-5764-7",
  url="https://www.fit.vut.cz/research/publication/11637/"
}
Files
Projects
Pokročilé paralelní a vestavěné počítačové systémy, BUT, Vnitřní projekty VUT, FIT-S-17-3994, start: 2017-03-01, end: 2020-02-29, completed
Relaxed equivalence checking for approximate computing, GACR, Standardní projekty, GA16-17538S, start: 2016-01-01, end: 2018-12-31, completed
Research groups
Departments
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