Result Details

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation

LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 244-251. ISBN: 978-1-5386-7376-8.
Type
conference paper
Language
English
Authors
Lojda Jakub, Ing., Ph.D., DCSY (FIT)
Podivínský Jakub, Ing., Ph.D., DCSY (FIT)
Čekan Ondřej, Ing., Ph.D., DCSY (FIT)
Pánek Richard, Ing., Ph.D., DCSY (FIT)
Kotásek Zdeněk, doc. Ing., CSc., DCSY (FIT), UTKO (FEEC)
Abstract

The complexity of today's systems is growing along with the level of chip integration. This results in higher demand for reliability techniques; it also increases the difficulty of incorporating reliability in such systems. For this purpose, we are working on a method to automate reliability insertion; however, for this method, it is necessary to have feedback on the result. In this paper, one component of the automation flow enabling the estimation of the resulting reliability - Fault Tolerance ESTimation (FT-EST) framework - is presented along with an improvement for accelerating the time necessary to reach the estimation. For the purpose of evaluation, we are using our Redundant Data Types approach, which enables us to intentionally insert reliability in a particular operation. The estimation utilizes the concept of fault injection. The results indicate, that the concept of Redundant Data Types is functional, however, also suggest its future improvements (e.g. for the operation of subtraction).

Keywords

Fault-Tolerant, Fault Tolerance Property Estimation, FT-EST, Verification, High-Level Synthesis, Redundant Data Type.

Published
2018
Pages
244–251
Proceedings
Proceedings of the 2018 21st Euromicro Conference on Digital System Design
Conference
21st Euromicro Conference on Digital Systems Design
ISBN
978-1-5386-7376-8
Publisher
IEEE Computer Society
Place
Praha
DOI
10.1109/DSD.2018.00053
UT WoS
000537466600037
EID Scopus
2-s2.0-85056474640
BibTeX 
@inproceedings{BUT155032,
  author="Jakub {Lojda} and Jakub {Podivínský} and Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}",
  title="FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation",
  booktitle="Proceedings of the 2018 21st Euromicro Conference on Digital System Design",
  year="2018",
  pages="244--251",
  publisher="IEEE Computer Society",
  address="Praha",
  doi="10.1109/DSD.2018.00053",
  isbn="978-1-5386-7376-8",
  url="https://www.fit.vut.cz/research/publication/11707/"
}
Files
Projects
IT4Innovations excellence in science, MŠMT, Národní program udržitelnosti II, LQ1602, start: 2016-01-01, end: 2020-12-31, completed
Pokročilé paralelní a vestavěné počítačové systémy, BUT, Vnitřní projekty VUT, FIT-S-17-3994, start: 2017-03-01, end: 2020-02-29, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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