Result Details

Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization

JOBRANOVÁ, S.; LENGÁL, O.; CHEN, Y.; CHEN, T.; JIANG, J. Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), October 27--31, 2024, New York, NY, USA. New York: Association for Computing Machinery, 2025. p. 1-9. ISBN: 979-8-4007-1077-3.
Type
conference paper
Language
English
Authors
Jobranová Sára, Bc., DITS (FIT)
Lengál Ondřej, doc. Ing., Ph.D., DITS (FIT)
Chen Yu-Fang
CHEN, T.
JIANG, J.
Abstract

Quantum circuit simulation is the basic tool for reasoning over quantum programs.
Despite the tremendous advance in the simulator technology in the recent years,
the performance of simulators is still unsatisfactory on non-trivial circuits,
which slows down the development of new quantum systems. In this work, we develop
a loop summarizing simulator based on multi-terminal binary decision diagrams
(MTBDDs) with efficiently customized quantum gate operations. The simulator is
capable of automatic loop summarization using symbolic execution, which saves
repetitive computation for circuits with iterative structures. Experimental
results show the simulator outperforms state-of-the-art simulators on some
standard circuits, such as Grover's algorithm, by several orders of magnitude.

Keywords

quantum circuit simulation binary decision diagrams symbolic execution loop
summarization

Published
2025
Pages
1–9
Proceedings
IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), October 27--31, 2024, New York, NY, USA
Conference
IEEE/ACM International Conference On Computer-Aided Design
ISBN
979-8-4007-1077-3
Publisher
Association for Computing Machinery
Place
New York
DOI
10.1145/3676536.3676711
BibTeX 
@inproceedings{BUT189135,
  author="JOBRANOVÁ, S. and LENGÁL, O. and CHEN, Y. and CHEN, T. and JIANG, J.",
  title="Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization",
  booktitle="IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), October 27--31, 2024, New York, NY, USA",
  year="2025",
  pages="1--9",
  publisher="Association for Computing Machinery",
  address="New York",
  doi="10.1145/3676536.3676711",
  isbn="979-8-4007-1077-3"
}
Projects
Efficient Finite Automata for Automated Reasoning, MŠMT, ERC CZ, LL1908, start: 2020-01-01, end: 2024-12-31, completed
Reliable, Secure, and Intelligent Computer Systems, BUT, Vnitřní projekty VUT, FIT-S-23-8151, start: 2023-03-01, end: 2026-02-28, running
Representing Boolean Functions by a Self-Adaptable Data Structure, GACR, Standardní projekty, GA23-07565S, start: 2023-01-01, end: 2025-12-31, running
Research groups
Automated Analysis and Verification Research Group - VeriFIT (RG VERIFIT)
Departments
Department of Intelligent Systems (DITS)
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