Result Details

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. p. 243-246. ISBN: 1424411610.
Type
conference paper
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Abstract

TBD

Keywords

digital circuit, polymorphic gate, adder, testing

URL
Published
2007
Pages
243–246
Proceedings
2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Conference
The 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
1424411610
Publisher
IEEE Computer Society
Place
Gliwice
BibTeX 
@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="243--246",
  publisher="IEEE Computer Society",
  address="Gliwice",
  isbn="1424411610",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf"
}
Projects
Methods of polymorphic digital circuit design, GACR, Standardní projekty, GA102/06/0599, start: 2006-01-01, end: 2008-12-31, completed
Security-Oriented Research in Information Technology, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, start: 2007-01-01, end: 2013-12-31, running
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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