Result Details

An Evolvable Combinational Unit for FPGAs

SEKANINA, L.; FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. COMPUTING AND INFORMATICS, 2004, vol. 23, no. 5, p. 461-486. ISSN: 1335-9150.
Type
journal article
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D., DCSY (FIT)
Friedl Štěpán, Ing.
Abstract

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.

Keywords

combinational circuit, evolutionary design, evolvable hardware, field programmable gate array

URL
Published
2004
Pages
461–486
Journal
COMPUTING AND INFORMATICS, vol. 23, no. 5, ISSN 1335-9150
BibTeX 
@article{BUT46258,
  author="Lukáš {Sekanina} and Štěpán {Friedl}",
  title="An Evolvable Combinational Unit for FPGAs",
  journal="COMPUTING AND INFORMATICS",
  year="2004",
  volume="23",
  number="5",
  pages="461--486",
  issn="1335-9150",
  url="http://www.fit.vutbr.cz/~sekanina/publ/cai/cai04.pdf"
}
Projects
Evolvable hardware based applications design methods, GACR, Postdoktorandské granty, GP102/03/P004, start: 2003-01-01, end: 2005-12-31, completed
Modern Methods of Digital Systems Design, GACR, Standardní projekty, GA102/04/0737, start: 2004-01-01, end: 2006-12-31, completed
Research groups
Evolvable Hardware Research Group (RG EHW)
Departments
Department of Computer Systems (DCSY)
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